Need skill file for net assignment

Have you tried using the Allegro 'Logic>Net Logic' functionality?

( You need to have the Allegro variable 'logic_edit_enabled' defined to enable it )

I m having 1000 pins need to swap with in that pin nets , avoiding manual work any idea

Here's a method to determine the ideal netlist to these components during routing and write a script that makes changes to the schematic. 

In the link below, I am sharing a Skill script and an Orcad CIS project to test.

This process needs temporary changes be made to the schematic. 

• Add temporary net aliases with TEMP prefixes to the connector/FPGA pins.   If you are using Orcad CIS, all TEMP net names/alias must have the same length.  Start with TEMP1000 as the first net name.
• Need to add the single-pin marker parts to the original nets on the schematic to be used to trigger the net rename.

Allegro has pad-to-pad DRCs having up to two net names in the error instance.   I'm using this to manage net alias changes.  It's fast.  Works with all versions. 

The process relies on adding single-pin temporary components to the schematic then placing them in layout to cause the DRCs.  The skill Script uses net assignments of the DRC errors to write schematic changes to an annotation script (net alias rename.)  Routing nets has no impact on this method; we only use pad-to-pad DRCs. 

After the schematic has been updated and verified, remove the temporary parts from the schematic, import the new netlist to the board and you should have clean routing and the project is in sync.  

The HDL annotation script for the schematic is exported but I have not been able to test it (I don't use Concept HDL.)   

Have not figured out a way to automatically handle diff-pairs, so those will need manual intervention at the schematic to correct the layout.

https://community.cadence.com/cadence_technology_forums/f/pcb-skill/47891/skill-method-to-optimize-netlist-pin-assignments-on-components-in-allegro-and-orcad-capture

Here's a method to determine the ideal netlist to these components during routing and write a script that makes changes to the schematic. 

In the link below, I am sharing a Skill script and an Orcad CIS project to test.

This process needs temporary changes be made to the schematic. 

• Add temporary net aliases with TEMP prefixes to the connector/FPGA pins.   If you are using Orcad CIS, all TEMP net names/alias must have the same length.  Start with TEMP1000 as the first net name.
• Need to add the single-pin marker parts to the original nets on the schematic to be used to trigger the net rename.

Allegro has pad-to-pad DRCs having up to two net names in the error instance.   I'm using this to manage net alias changes.  It's fast.  Works with all versions. 

The process relies on adding single-pin temporary components to the schematic then placing them in layout to cause the DRCs.  The skill Script uses net assignments of the DRC errors to write schematic changes to an annotation script (net alias rename.)  Routing nets has no impact on this method; we only use pad-to-pad DRCs. 

After the schematic has been updated and verified, remove the temporary parts from the schematic, import the new netlist to the board and you should have clean routing and the project is in sync.  

The HDL annotation script for the schematic is exported but I have not been able to test it (I don't use Concept HDL.)   

Have not figured out a way to automatically handle diff-pairs, so those will need manual intervention at the schematic to correct the layout.

https://community.cadence.com/cadence_technology_forums/f/pcb-skill/47891/skill-method-to-optimize-netlist-pin-assignments-on-components-in-allegro-and-orcad-capture