Pin Swap issue from DE HDL to System Capture

Dear all,

i imported a DE HDL Project into System capture. here i got two issues. This is FPGA design with pinswaps.

The first issue is that after converting the last status of the fpga symbol(some pins are swapped) is not placed in the schema and instead of that the symbol came from the lib without pin swapping. Is it possible to solve this issue?

furthermore i clicked the resolve button and made the first update to layout. I got the net error because all the changes of the pin swapping were removed. I made the pin swap on one pin as test again and made the backward annotation to schema.

i got the 2. issue.  I realized that only the Pin Number was swapped but the Pin Name didn't swapped. In DE HDL the pin name swapped with Pin Number together. Is this issue depend on any settings of the system capture?

The Pin Number Y1 in DE HDL Schema is correct after swapping

In the system capture the Y1 with the wrong Pin Name after backwards annotation.

Many thanks and best regards

Moyan