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Simplifying ratsnest to a connector or FPGA during routing and update the schematic. I shared a Skill script.

Robert Finley

https://community.cadence.com/cadence_technology_forums/f/pcb-skill/47891/skill-method-to-optimize-netlist-pin-assignments-on-components-in-allegro-and-orcad-capture

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  • jc teyssier
    0

    Sound good. Thank your for sharing. Too late for my actual design but maybe i will have a try on next one using fpga Slight smile

    Jean-Charles from France

  • RFinley
    0 in reply to jc teyssier

    Thank you for letting me know.   

    It exports scripts for Concept HDL and Orcad Capture. 

    I am struggling to capture a schematic in Concept due to library issues, so I can't verify the HDL export is correct.   

    Anyone gets it working, please let me know.

Reply
  • RFinley
    0 in reply to jc teyssier

    Thank you for letting me know.   

    It exports scripts for Concept HDL and Orcad Capture. 

    I am struggling to capture a schematic in Concept due to library issues, so I can't verify the HDL export is correct.   

    Anyone gets it working, please let me know.

Children
  • jc teyssier
    0 in reply to RFinley

    I will.

    Oru primary flow is with Orcad Capture (say... 99% of designs) a verry few design are done with Concept. I will prefer the exact opposite but choice is not myne.

  • RFinley
    0 in reply to jc teyssier

    System Capture offers the best of HDL with similar library of Orcad CIS.  Easier to deploy for smaller companies than HDL, I think.

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