Some net names are missing in netlist file generated in DEHDL

To resolve the issue of missing net names such as "VCC" and "PBKG" in the netlist file generated using Cadence Allegro DE HDL, you can follow a systematic approach. First, ensure the nets are correctly named and assigned in the schematic editor. Verify their connectivity using tools like Highlight Net or Browse Nets to confirm that they are not floating. If aliases are being used, check that they are properly assigned and do not conflict with the original net names. Next, review the test point settings, as the report indicates that only test points like "TP_VCC_S1" and "TP_PBKG_S1" are included. Adjust the netlist generation settings in Netlist Reports Settings to include all nets, not just test points. Refresh the design database using Tools -> Packager Utilities -> Update Design and regenerate the netlist to ensure all connections are updated.

Inspect the filters applied during netlist generation to ensure no exclusions are causing the issue. If a customized netlist template is being used, confirm that it includes sections for all net types, including power and signal nets. Running an Electrical Rule Check (ERC) can also help identify any warnings or errors related to connectivity or naming. Open the generated netlist file manually and search for the missing nets to confirm whether they are being excluded due to formatting or reporting settings. 

If the issue persists, reaching out to Cadence support can provide further assistance. By carefully reviewing the schematic, settings, and generation process, you can resolve the issue and ensure that all net names are included in the netlist report.