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Design Entry HDL error spcocd-152

VC202503176623

Hi,

I got a error about the "error (spcocd-152): Port SWDIO in cell 'adapter_jlink' is missing in block

Please advise what's the message mean for, and how to resolve this problem, thanks

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    The SPCOCD-152 netlisting error is reported when saving the schematic in DE-HDL. The problem occurs due to one of the following reasons:

    • If the hierarchal symbol does not have a H-pin corresponding to a port placed in its design.

    OR

    • When the entity/verilog.v file of the part is incomplete. This file is incomplete because master.tag files are missing for this part.

    As the error messages suggests, the problem can occur if new ports were added in the design referred by the hierarchical symbol (H-block), but a new symbol was not generated.

    To resolve the error, open the H-block design and go to Tools > Generate view to create the new H-block.

    Now, the H-block placed on the top-level design will have the required ports.

    If this does not help, try to run the following tool to generate master.tag files and fix the issue:

    con2con -proj <cpmfile> -cdslib <path to cdslib> -lib <source lib of cell> -cell <name of source cell> -product PCB_Librarian_Expert

    You can access this info using following article link on Cadence ASK portal:

    Article (20480125) Title: ERROR(SPCOCD-152): Port on instance does not exist in entity declaration for instance
    URL: support.cadence.com/.../ArticleAttachmentPortal

Reply
  • 0

    The SPCOCD-152 netlisting error is reported when saving the schematic in DE-HDL. The problem occurs due to one of the following reasons:

    • If the hierarchal symbol does not have a H-pin corresponding to a port placed in its design.

    OR

    • When the entity/verilog.v file of the part is incomplete. This file is incomplete because master.tag files are missing for this part.

    As the error messages suggests, the problem can occur if new ports were added in the design referred by the hierarchical symbol (H-block), but a new symbol was not generated.

    To resolve the error, open the H-block design and go to Tools > Generate view to create the new H-block.

    Now, the H-block placed on the top-level design will have the required ports.

    If this does not help, try to run the following tool to generate master.tag files and fix the issue:

    con2con -proj <cpmfile> -cdslib <path to cdslib> -lib <source lib of cell> -cell <name of source cell> -product PCB_Librarian_Expert

    You can access this info using following article link on Cadence ASK portal:

    Article (20480125) Title: ERROR(SPCOCD-152): Port on instance does not exist in entity declaration for instance
    URL: support.cadence.com/.../ArticleAttachmentPortal

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