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Simulation of internal terminated LVDS inputs with SigXplorer

florian

 Hi,

 

I'm simulating a PCB with a Xilinx V5 FPGA and generated therefore IBIS models with ISE. Some of the LVDS inputs have internal termination (Attached below is the IBIS file section where the termination is defined). But after importing the IBIS model into the dml format there is only the LVDS_25 model available. I can use them as differential input, but there is no option to set internal termination. Has anybody a idea to solve this?

 Thanks,

 Florian 

 

| LVDS receiver with internal differential termination
| (use as input only)
166P    LVDS_25_DT_P    LVDS_25
166N    LVDS_25_DT_N    LVDS_25

[Series Pin Mapping] pin_2    model_name     function_table_group
|
166P          166N        rterm_100
|
|************************************************************************
|                       100ohm differential resistor
|************************************************************************
|
[Model]          rterm_100
Model_type       Series
|                         (typ)               (min)               (max)
|
C_comp                    0.0000pF            0.0000pF            0.0000pF
[Temperature Range]       25.0000             85.0000             0.000
[Voltage Range]           2.5000V             2.3750V             2.6250V
[R Series]                103                 126                 81
|
 

  • Khurana

    What's your real question?  What do you want to do?

  • florian

    I would like to simulate a LVDS Bus on my PCB (check crosstalk,  signal integrity) . All the differential pairs have NO 100 Ohm resistor in the net and therefore not in the topology, because I use the internal (on die) termination of the device.

    To reach realistic results I need the termination resistor included in the  IbisInput model. My real question is: How can I include this resistor in the SigXplorer IbisInput model?

    Did I make myself clear?

  • Khurana

     Yes, you did.  Am not certain if the following will work but try it out.

    What's the name of the input buffer model as defined within the IBIS model?  Is it rterm_100?  If yes, in SigXplorer, go to Edit > Part > change the filter to IbisInput > select to place it on SigXP canvas.

     

  • florian

    The name of the LVDS input buffer (without termination) is LVDS_25. After extracting the topology this model occurs in the DiffInput Symbol.

    rterm_100 is the termination resistor model. As you can see in my first post: In the ibis model description, the resistor is connected to the diff pairs model (pin mapping 166P and 166N). But now in the dml this information is missing.

     I tried your idea but in SigXplorer PCB SI XL 16.0 there is no Edit->Part->change the filter to IbisInput option. What exactly does change the filter to IbisInput mean?

     

     

  • Khurana

    Hmm...sorry...should have said Edit > Add Part...Edit is the menu pick in SigXplorer (i.e. click Edit > select Add Part).  This brings up the Model Browser.  Now, ignore what I said previously.

    To include the terminating resistor, change filter to ESpiceDevice and for name pattern enter asterisk.  You should now see the terminating resistor model (which is in the IBIS model) - the name is  rterm_100.  Add this to the topology and hook it up between p and n pins of the receiver, which in this case is LVDS_25.

    I think that's how you do it - makes sense?

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