Defining relative propagation delays

 I think you're on the right track.  Perhaps you might want to match differently...  that's for a later exercise. But if I read what you're saying you want, you should do the pin pairs like you state.  Did you enable the mode that checks relative propagation?  It defaults to off....

 So I have created a test project to see if we're on the right track.  Take a look. It is just for a reality check....no real symbols were harmed in the creation.  I think it gets the message across.

 With this as a template, let me know what works/doesn't work.

Bill

You can do this in OrCAD Capture v15.2 or higher.  Select the nets > right click > select Properties > go to Flat Nets tab > left click in Relative Propagation Delay tab > right click > Invoke UI (or something like that).  This will pop up Relative Propagation Delay window.  You can create the rule there by specifying the pin pair and delta/tolerance values.  Then, you can copy and paste the property value to other cells for the nets in the match group.  There should be a video on this - search for this in OrCAD Capture Help.

You might also want to look at a tool named MakeCAP - more info at http://www.ema-eda.com/products/other/makecap.aspx.  The tool bolts on to OrCAD Capture and gives you the ability to create/assign high speed properties for Allegro PCB Editor.

Bill,

Thanks for the input.  As an FYI, I only have OrCAD capture CIS installed on my system, not Allegro.  Our board designs are contracted out which is why I'm trying to define my delays in CIS.

In any event, I used a viewer to take a look at your template and the dummy layout is exactly my situation.  Let's move to some syntax and see if we can iron out some proper propagation delays.  Let's use J1, U2 and U3 as in your dummy layout.

First off, I define some propagation delays for each clock.  Let's assume the clocks are connected as J1-1 to U2-1 and J1-2 to U3-1.  My constraint is that each clock could be a minimum of 0.5" and a maximum of 4".

PROPAGATION_DELAY (CLK1) = J1.1:U2.1:500 mils:4000 mils

PROPAGATION_DELAY (CLK2) = J1.2:U3.1:500 mils:4000 mils

Let's now define the clocks as targets for matching:

RELATIVE_PROPAGATION_DELAY (CLK1) = PCI_CLK1:G:J1.1:U2.1::

RELATIVE_PROPAGATION_DELAY (CLK2) = PCI_CLK2:G:J1.1:U3.1::

Now let's take, as an example, PCI data/address line 0 (net name = PAD_0).  Let's assume that it's connected from J1-3 to U2-2 and U3-2.  Net PAD_0 has two pin pairs; J1-3 to U2-2 and J1-3 to U3-2. 

This is the point where I would like to create some relative propagation delays using each clock as a target.  To do this I would have to have net PAD_0 included in both matched group PCI_CLK1 and PCI_CLK2.  I can't seem to do this.

Can you comment any further?  Am I not defining things the right way?

Thanks,

Steve

I don't know what level license you have for OrCAD but I can not (never have) been able to set up the constraints you're doing in OrCAD.  I use Allegro exclusively for that.  But what you are asking for is AOK.  The CM in Allegro allows pin pairs to include the same pin multiple times for pin pairs.  I changed the setup (like I was hinting at in the last post) to what I think you're asking for.  

Take a look at the net_constraints.txt file in my zip and you can see a text view of the setup I have to meet the conditions you're asking for.

When I backannotate to OrCAD it pushes only the rel propagation property back to the clocks since it's not on a pin-pair.

See if this is what you desire -- not sure how you enforce constraints from OrCAD with your 3rd party layout.  It's all internal here and Allegro is the central control point for constraints.  

Ping back if you have more questions after looking at the files I sent

Bill

I took a look at the constraints.txt file and that's exactly how I want to set up my constraints.  I'll have to contact support or perhaps hear from someone else on the forums as to whether I can actually do this in Capture rather than Allegro.

Thanks for the help, it's much appreciated.

-Steve