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importing FPGA design into Design Entry HDL

bdatta

 Hi,

Im trying to take a design from Altera quartus for an FPGA using LVDS differential IO pins.  But when I import the design into Allegro part developer the part that is produced only has single pins for the IO, no differential pairs.  Am I doing something wrong in Quartus or in the Allegro Part developer?

  • redwire

     If I understand your question correctly, the part developer does not keep track of diff pairs -- you do.  You need to apply the property to the net pair and it will forward into Allegro.

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