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Use of a "null" padstack

microsoftpc
Before release 16.0, we used a null padstack. The null padstack was used as a placeholder padstack on a surface-mount connector in which certain pins are not used , for keying purposes. In some other cases different pins were not used and/or a different number of pins were not used. They were all alternate symbols for the same part number component. Alternate symbols for the same default symbols must have the same number of pins. For example, on a 24-pin connector, pins 23 & 24 may not be used, where on another alternate, pins 1,3 & 5 may not be used. Before, I was able to define the null padstack by creating a definition on a non-electrical layer that was not used, for example, FILMMASK_TOP. There, no DRC's would appear on any electrical layers. This worked well when producing gerber files and ipc356(not ipc356A) netlist that were checked in Valor. IPC356A is not translatable in Valor.

Now, in release 16.0 and above, padstacks are now required to have some kind of definition on an electrical layer. If I define anything on a electrical layer, even as a circle shape with no dimension, DRC’s will occur as in its spot to a plane or trace or via.

Cadence responded this to my situation: The electrical symbol would has to match the physical. That being said the physical has 22 pins, either pins 1/3 missing or 23/24.You would then need the elec. to have the same pins missing. If you want the ipc netlist to come out - and meet the spec - then you will need several sym sets. I don't believe there is a 'one size fits all' answer here.
Has anybody used a padstack in the same situation that I described in rel 16.0 and above? If so, how did you define the padstack? Was there  any DRC's as a result? Any suggestions would be much appreciated.
  • mcatramb91

    Hello,

    I had similar situation in the past but I have always had a pad on one of the electrical layers.  I do have a suggestion which may help.  Why not just use a smaller padstack to achieve the same result for the pins which are not present, something like a small smt pad or pad with a drill which can have the pin number associated to it.  I attached an example of what I am talking about in an edge connector situation.  Now this may not work with your particular surface mount connector but may be a good alternative for you.

    Hope this helps,
    Mike Catrambone

  • fxffxf

    assuming you are using 16.2 set the env variable padstack_allow_null toallow no etch layers in padstacks

  • pcbgeorge
    We just upreved the old null pad, which worked :)
     
    Be aware, 16.01 has a problem in the IPC Netlist when using null pads.  It gives it a through-hole code, then doesn't give it a drill field, so it causes a syntax error in the Valor netlist analyzer.  In versions before 16 it gave it a SMD code, since it was using a null drill size, which was accepted by Valor without problem.
     
    I have an SR (41519380) on this problem now...
  • microsoftpc

    Yes, that is where I first noticed what was going on. I thought that the format of the ipc356 netlist was changed in rel 16.01. I opened SR #41413618 and have since then narrowed the problem to the "null" padstack after several hotfixes assigned and failed on this issue. The Cadence response that I posted is their stand on this. Can you please keep me posted on the results from your SR as Cadence stance on "null" padstacks is "do at your own risk".

  • microsoftpc

    This is what I have set in my env file for rel 16.2:

    set padstack_allow_null

     However this still not allow me to save the "null" padstack as a single layer padstack. Perhaps that is the wrong syntax. If it is the wrong syntax can you show me the correct way, thanks.

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