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About the io wire resistance?

whlinfei

 Hi All,

 I am designing a class D amplifier using ibm 130nm pdk. 

I try  to simulate the connecting wire between the chip and its package io pad. But I couldn't find any data on the normal resistance and inductance under this process.

Can anyone help me on this or tell me where I could look into?

Thanks a lot!

Best Regards,

Whlinfei 

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