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Creating Pin Pair

Mstrghettorigg
Hello All, I was wondering if there was more efficient way to create pin pair rather than doing it one net at a time on the constraints manager. I am currently clicking on each net and selecting the both end of the connection. EX| U1.1 and J1.1, U1.2 and J1.2, etc. This takes significant amount of time and I was wondering if there was easier way to make pin pairs. For example, assigning pin pair for between two components U1 and J1 by bus group property. Also, when import the logic and if there a change in connection or net name then the pin pair is lost. I was also wondering if there was anyway to prevent losing the pin pairs when there are changes in the netlist. Please let me know if anyone has better method of creating pin pairs than doing it one by one. Thanks!

  • I am assuming that this would be for a matched length group. The format for the constraint is [group name]:{global/local(G/L)}:[device.pin]:[device.pin]:(delta):(tolerance).The pin pairs can be made generic by replacing the [device.pin]:[device.pin] with L:S for longest to shortest, or D:R for driver to receiver, or AD:AR for all drivers to all receivers. This is covered in more detail in the commands manual. If the group is already established in the constraint manager, clicking in the box under the Pin Pairs column will reveal a drop down menu to select the generic of your choice. You can also click on the first box of the group, hold the mouse button and drag to the last box of the group to select the entire group to make your selection for the entir group at one time.

    Making the pin pairs generic will allow changes to the net without the necessity to recreate the pin pair in the group. It is best to place these constraint values on the net at the schematic level to avoid having them removed or changed when you read in a new netlist or constraint file.

    Regards,

    Harold Pattie

    harold.pattie@ericsson.com

     

  • Very simple.   You have two options:

     1) Create one pin pair inside Min/Max Prop Delay worksheet in Nets folder then specify min/max values for the pin pair.  Then, select the Net (which contains that newly created pin pair - do not select pin pair) > right click > Create > Electrical CSet.  Select other nets that you want to create pp for > right click > select > Constraint Set References > select the ECSet name from drop down at top.

     2) Extract topology in SigXplorer and define pp using Set > Constraints.  Then, either save the topology file or click File > Update Constraint Manager - this imports the topology file as an ECSet.

     I believe option 1 requires Allegro PCB XL and option 2 does require SigXplorer (no SI) which I believe comes with Allegro PCB XL i.e. I don't think you can do this with Allegro Performance.

  • Thank you.  I'll try it when I get to work tomorrow.
  • Hello,

    Option 1 worked perfectly!  Thank you!
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