REGARDING MICROViA

Current carrying capability is the least of your problems. 

Right now, you need to find a way to hook this up with as few a number of laser via layers as possible.  

Is this some kind of FPGA I haven't heard of yet?

1249 pins, sqrt of that is about 36 x 36.  With half the pins being ground, that means 9 channels around the perimeter of the device.  

How big is your board going to be?   Who do you believe will fabricate this?   Better yet, where are your VDD pins?

If this device has any impedance-controlled traces because of high-speed signals, you have to design for a low-impedance grounds which means you will need buried ground vias very close to your signal balls or the board won't work.

I would work on fanning out the device to see how many signal layers you have.  I have been forced to design a board where the first ground plane was on layer five.  Yes, that is four lamination steps for the fabricator.  Why?  Because they had to fit four boards on a standard panel size or the cost constraint couldn't be met.  (whatever...)   Yup.  I had adjacent layer crosstalk like crazy that had to be fixed.  But, it allowed the board to route 100%.

 This is a high speed impedance controlled board with very tightly packed components(board dimension:70x80mm),the BGA (22x22mm),all pins are used.

Thanks for your reply & suggestion.

Regards

Girish Kumar 

Well, your board size ('bout 3" square) helps me feel better..

I implore you to ask the device manufacturer for any information on verified methods for fanning this out (we called them route studies). 

If you have to fan out every single one of those ground balls to a buried via, I will be happy I am not doing it.  But, if the chip design allows you to skip a GND ball when necessary, it will help. 

For impedance-controlled traces going to internal layers through core vias, you need to minimize parasitic inductance (loop area) which means signal and ground core vias close to each other, tying ground planes together.  More ground core vias will improve performance up to the point where they chop your VDD planes.  Mitigate that by seeing if you need all the ground balls connected..

I understand why signal 2 is attractive for a ground plane.  But, you may have an easier time breaking the first two rings of signal pins out if you push the first ground plane to layer 3 or 4, as long as you leave room to keep adjacent layer signal shadowing to a minimum. 

Keep in mind the handset industry relies heavily on Panasonic's ALIVH and DDi's Stacked Microvia Technology for 0.4mm pitch devices.   Check with them on turnaround times as DDI is *very* popular for this technology.

While 0.4mm devices are what my former employer developed for the wireless handset industry, we never have a solid array of balls like you have.  

Fortunately, I think you are using Allegro, which has excellent DRCs for adjacent layer parallelism.   I worked for a Mentor shop.  We didn't have any adjacent-layer DRCs for crosstalk unless we translated the Boardstation database to Allegro XL and ran DRCs there.