Why PI Design is More Difficult Than SI

Why PI Design is More Difficult Than SI

source: PCB Partner

Anyone practicing it can tell you that power integrity (PI) design for high-speed digital circuits is getting increasingly difficult in these days.

At first it was all about functionality. Lower-speed digital electronics designers only had to care about hooking up the components properly. Designs were schematic-based, and the physical implantation - PCB stackup, component placement and layout - mattered very little. At higher speeds, signal integrity (SI) issues emerge: We have to make sure that digital signals arrive on time and with low enough distortion.

SI work means doing time of flight, skew and timing analysis and checking reflections, matching, crosstalk, attenuation and dispersion of signals.With increasing speed and system density, power integrity (PI) issues also become very challenging.
Exploding Number of Supply Rails

Sometimes we hear the argument that PI is more difficult because we have an exploding number of independent supply rails to deal with. Ten or twenty years ago, systems had one, two or maybe three different supply rails. But large computer boards today may have up to several dozen independent supply rails. This is a big challenge, indeed. However, the number of supply rails is still many times lower than the number of high-speed interconnects, so this alone can not explain why PI is more difficult than SI.
Instead of 1D, it's a 2D or 3D Problem

SI design is mostly a one-dimensional problem. We know where the main signal goes: Along the narrow, long traces that we design. The traces determine the path of the signal. A major contributor to the PI challenge is the fact that a PDN is usually two-dimensional, and sometimes even three-dimensional. Noise on planes can propagate anywhere in the X-Y directions and vias can carry the PDN noise in the Z direction as well. Also, we don't design the PDN to intentionally propagate the noise; to the contrary, a well-behaved PDN should block the propagation of noise as much as possible. To figure out how noise spreads, we need 2D or 3D PDN models, which are harder to create and manage than a 1D SI model.

Unknown Excitation, Uncertain Requirements
In SI, we usually know what the signal level and waveform are supposed to be. The "main" signal for PI is the PDN noise excitation, but unfortunately its exact nature is mostly unknown to board designers. Noise excitation entering the PDN could come from a number of sources: Power converter ripple and burst noise, shoot-through switching-current spikes of active devices and - last but not least - return currents of signals. Two of these four contributors, the converter burst noise and the shoot-through current spikes of active devices, are usually not - or just very vaguely - specified, so designers have very minimal input for a systematic PDN design.