Stats

Locked Locked
Replies 1
Subscribers 165
Views 13493
Members are here 0

error when ctreating netlist in capture CIS 16.2

hi all,

im using allegro16.2, and i getting an error when creating netlist for PCB Editor, the error details are given below, please anybody help me to clear the error.

ERROR(SPCODD-433):
Error at line 820 in file <dir>\allegro/pstxnet.dat. Error in syn

The error line is:

819: NODE_NAME U3 8

820: '@<project name>.SCHEMATIC1(SCH_1):INS275078@SCHLIB.AS1108.NORMAL(CHIPS)':
821: 'DIG 1':;

regards

Anand

Parents

oldmouldy over 15 years ago

Your name "DIG 1" is illegal since it has a space in it, "DIG1" would be legal and work correctly.
Cancel
Vote Up 0 Vote Down

Cancel

Reply

oldmouldy over 15 years ago

Your name "DIG 1" is illegal since it has a space in it, "DIG1" would be legal and work correctly.
Cancel
Vote Up 0 Vote Down

Cancel

Children

No Data

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.