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$pnn property

ahmetozsoy
ahmetozsoy over 15 years ago

Hi,

I am using DE HDL 16.3 and PCB Editor 16.3

I am having a trouble with $pnn property. How and where  is it come from?  I only assign a net to a pin in PCB editor ( By Using NET LOGIC ) and in project manager find diff and update schematic But when updating the sch it puts '_1' to the end of the net name and a $pnn property was added. 

I want to get rid of this. How can achieve this issue.

Thanks in advance.

Ahmet OZSOY

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  • EvanShultz
    EvanShultz over 15 years ago

     PNN = Physical Net Name

     

    In a hierarchical schematic, each replicated block will have the same net names. For example, if you have three blocks they might each contain NET1, NET2, and NET3.

    The PCB can't handle different nets having the same name, so Packager assigns a PNN to each of the nets. This is typically the existing name of the net, plus some separator character and a suffix character(s). By default, the separator character is an underscore and the suffix character(s) are a single number, so the PNN for NET1 might be: NET1_1, NET1_2, and NET1_3. In this fashion, you can see the "base" net name and also tell which block a particular net is from.

    You can select the suffix character(s) by placing the SUBDESIGN_SUFFIX property on a block. Otherwise it's chosen for you. The separator character can be selected on the Subdesign tab of the Packager Setup form accessed from the Advanced button of the Export Physica form.

    On the Layout tab of the same Packager Setup form, you can uncheck the Physical Net Name box to prevent the PNN property from being annotated to the schematic. PNN is still conjured by Packager, it will just not be sent to the schematic. This can be terribly confusing because then you don't know which of the 3 NET1s you could be looking at on the board. Just a warning.

    So to bring it back home, I don't think you can get rid of this property but you can suppress it from showing up on the schematic.

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  • ahmetozsoy
    ahmetozsoy over 15 years ago

    Hi,

    I have just solved my issue. Yes you are right. I have a hierarchy design and nets are not global so in PCB side when I assign a net and the updade the sch. it passes this to a net and the other ( which I have noticed later that these nets are not global where I assume them to be the same net ) net takes  a '_1' at the end.

    Thank you for your explanation.

    Best regards

    Ahmet OZSOY 

     

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  • maberu
    maberu over 9 years ago

    Hi Ahmet OZSOY,

    How were you able to resolve the issue?  How can I make a connection between NET1, NET1_1 and NET1_2?

    Thanks,

    Maberu

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