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OrCAD PCB Editor without schamatic

Aey2519

 Can design pcb in orcad pcb editor without capture drawing. can i place symbol and add connection in pcb editor.

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  • Rik Lee

    One of the easier ways to create a logical netlist for small circuits is to type up a 3rd party netlist in a test editor.

    It consists of three parts with delimiters

    1. $PACKAGES section - This contains the Allegro symbol type, the device file name followed by the refdes.

            allegro_symbol_name ! device_file ; refdes1 refdes2 refdes3
           
    2. $NETS section - This contains the logical connectivity with NETNAME and then refdes.pin refdes.pin refdes.pin
           
            neta ; U1.1 U2.1 U3.1
            netb ; U1.2 u2.2 u3.2
           
    3. $END


    Example:

    $PACKAGES
    DIP14 ! 'MYPRME-1' ; K1
    SIP8 ! 'MYPUPRES-2' ! 2K ! '10%' ; R1
    $NETS
    '-MTCAS' ; R1.3
    '-PRE' ; K1.6 R1.8
    A ; R1.7
    B ; R1.6
    C ; R1.5
    GND ; K1.7 K1.8
    Q1 ; K1.2 R1.4
    Q2 ; R1.2
    VCC ; K1.1 K1.13 K1.14 R1.1
    $END


    From File > Import > Logic select the "Other" tab. Browse for the netlist -  if you are updating a design select 'Supersede all logical data' - then select "Import other"

    You can also export a netlist form a board that has logical data in it from File > Export >Netlist w/Properties to get a netlist and modify that to change connectivity. Any connectivity changes should also be made in the schematic - if there is one- so the design is in sync.

Reply
  • Rik Lee

    One of the easier ways to create a logical netlist for small circuits is to type up a 3rd party netlist in a test editor.

    It consists of three parts with delimiters

    1. $PACKAGES section - This contains the Allegro symbol type, the device file name followed by the refdes.

            allegro_symbol_name ! device_file ; refdes1 refdes2 refdes3
           
    2. $NETS section - This contains the logical connectivity with NETNAME and then refdes.pin refdes.pin refdes.pin
           
            neta ; U1.1 U2.1 U3.1
            netb ; U1.2 u2.2 u3.2
           
    3. $END


    Example:

    $PACKAGES
    DIP14 ! 'MYPRME-1' ; K1
    SIP8 ! 'MYPUPRES-2' ! 2K ! '10%' ; R1
    $NETS
    '-MTCAS' ; R1.3
    '-PRE' ; K1.6 R1.8
    A ; R1.7
    B ; R1.6
    C ; R1.5
    GND ; K1.7 K1.8
    Q1 ; K1.2 R1.4
    Q2 ; R1.2
    VCC ; K1.1 K1.13 K1.14 R1.1
    $END


    From File > Import > Logic select the "Other" tab. Browse for the netlist -  if you are updating a design select 'Supersede all logical data' - then select "Import other"

    You can also export a netlist form a board that has logical data in it from File > Export >Netlist w/Properties to get a netlist and modify that to change connectivity. Any connectivity changes should also be made in the schematic - if there is one- so the design is in sync.

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