Effect of shapes on Impedance and Board

You are correct that every layer of every board would benefit from even copper distribution from board edge to board edge. 

This improves the chances your board shop will have uniform electro-plating on the traces and in the holes in all areas of the board.  Uneven copper distribution for plating makes that job more difficult and probably will be one of many contributors to warp.

 However, you have to be careful to keep from harming impedance controlled trace widths determined by the dielectric thickness relative to the reference plane (usually ground). So, you have to be super careful with shapes.

If layer 3 is a ground plane, 1 and 2 are signal, the safest way to solve the copper distribution and plating problem is to use small thieving pads.  The key here is to not use a large single piece of copper pour as if you don't connect it to a DC power/ground net, it will pick up noise from one part of the board and spray it into other parts.

Thieving pads are small enough to be left floating and have negligable effects on adjacent traces.   5mm square should suffice.

 Another common mistake with ground fill is allowing it to be too close to the signal.  We call this edge(not broadside. oops) coupling.  It will cause an impedance dip and excess parasitics that are not very nice to fix on the bench.  More ground isn't necessarily a safe option. 

 My favorite approach however is to tell the fabrication house to use their CAM tools to put the thieving on during panelization.  Make this part of the fab drawing instructions.  I would specify that thieving be kept at least 7.5mm away from active signal traces even on adjacent signal layers, if that is possible.  

Moving thieving around for an ECO is time consuming and really needs to be avoided.

 Another thing to keep in mind, especially in sequential lamination, is that it is very advantageous to have thieving on layers that go through the plate and drill process, but might not be so critical if they are internal signal layers.

You are correct that every layer of every board would benefit from even copper distribution from board edge to board edge. 

This improves the chances your board shop will have uniform electro-plating on the traces and in the holes in all areas of the board.  Uneven copper distribution for plating makes that job more difficult and probably will be one of many contributors to warp.

 However, you have to be careful to keep from harming impedance controlled trace widths determined by the dielectric thickness relative to the reference plane (usually ground). So, you have to be super careful with shapes.

If layer 3 is a ground plane, 1 and 2 are signal, the safest way to solve the copper distribution and plating problem is to use small thieving pads.  The key here is to not use a large single piece of copper pour as if you don't connect it to a DC power/ground net, it will pick up noise from one part of the board and spray it into other parts.

Thieving pads are small enough to be left floating and have negligable effects on adjacent traces.   5mm square should suffice.

 Another common mistake with ground fill is allowing it to be too close to the signal.  We call this edge(not broadside. oops) coupling.  It will cause an impedance dip and excess parasitics that are not very nice to fix on the bench.  More ground isn't necessarily a safe option. 

 My favorite approach however is to tell the fabrication house to use their CAM tools to put the thieving on during panelization.  Make this part of the fab drawing instructions.  I would specify that thieving be kept at least 7.5mm away from active signal traces even on adjacent signal layers, if that is possible.  

Moving thieving around for an ECO is time consuming and really needs to be avoided.

 Another thing to keep in mind, especially in sequential lamination, is that it is very advantageous to have thieving on layers that go through the plate and drill process, but might not be so critical if they are internal signal layers.