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make a different net constraint inside constraint region

andri26

Hello,  I need some help in cadence. actually i just learning cadence allegro PCB editor now.

I'm on my way to route Broadcomm decoder to DDR3 component. I have set constraint region to make my default line width = 0.1 mm for signal wire. but in BGA there are so much power wire which need wider line width (like 0.2 mm or wider). can I set my net constraint for power in my contraint region? and how?

 

thanks for your help
  • Mashak

     You can set a different set of constraints in the region defined.

    Use constraint manager help supplied by cadence......

     The process is long to explain.

  • Ejlersen

    Hi

    You can put nets in a net class (select nets and right click, create, net class)

    Now you can create a region-class relation between your region and the newly created netclass. Now set the width of the region-class object and you should be set to go.

    Best regards

    Ole

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