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Problem creating PSpice Model Containing subckt (subcircuit)

rockiesmike

I'm using rev 15.7 

The question I have if I'm converting a text spice model that contains subckt correctly?  The circuit will not converge. One of my components that the circuit is built around spice model entered below contains subckt (subcircuits).  The process I went used to convert the spice model vendor text file was using the Model Editor which converted only the first subckt.  I then pasted in the rest of the missing bottom subckt while in the Model editor.  When I save it the editor breaks out the bottom subckts under the model list on the left.  I place the part and check its pspice model it only contains the first root subcircuit.  Yes, I did add the library file to the configuration.  The vendor app guy claim this model works for him and he sent me a netlist of his test circuit. I believe he is using a different spice tool.  I've tried rebuilding his netlist and get the same result.  His netlist shows this model with all the subckts.  So am I creating the spice model correctly or is it possibly my circuit is in error?

 * ACPL-332J SPICE Macromodel
* Rev. A
* 11/07
* ZFC
*
* This is the behavioural model for the above-mentioned part number.
* It is valid for functional simulation over the range specified below.
* Temperature = 25C
*
* Macromodels provided by Avago Technologies are not warranted
* as fully representing all of the specifications and operating
* characteristics of the product.
*
* Macromodels are useful for evaluating product performance but they
* cannot model exact device performance under all conditions, nor are
* they intended to replace breadboarding for final verification.
*
* Copyright 2007 Avago Technologies Limited. All Rights Reserved
********************************************************************************
* This is       pin1               to              pin16
*                |                                    |               
.subckt ACPL332J 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 
xicc2 9 13  icc
xldlogic3 9 130 38 57 32 53 or3
xldlogic 9 130 51 52 53 50 and3
xlimitl 9 50 54 limitl
xhlimit 9 40 45 limit
xhdlogic 9 130 41 34 43 44 40 and4
xocplogic2 9 130 35 32 36 or2
xled_drive 9 34 8 6 led
xled_fault 1 22 9 15 led
xinver_clamp 9 130 344 83 inverter
xldlogic4 9 130 34 57 inverter
xldlogic2 9 130 56 52 inverter
xldlogic1 9 130 40 51 inverter
xhdlogic3 9 130 50 44 inverter
xhdlogic2 9 130 32 43 inverter
xhdlogic1 9 130 38 41 inverter
xocplogic3 9 130 34 35 inverter
xclamplogic 9 130 82 83 84 and2
xldlogic5 9 130 11 32 56 and2
xocplogic4 9 130 31 344 390 and2
xrs_clamp 9 130 344 81 82 r_s
xrs_desat 9 130 33 390 32 r_s
xcompa_clamp 9 130 10 80 81 comparator
xfaultreset 9 130 92 91 33 comparator
xocp 9 130 30 14 31 comparator
xuvlo 9 130 13 377 38 comparator
xfault_delay 1 23 212 211 21 comparator
efaultdrive 24 1  21 1 1
efault 210 1  22 1 1
edsatshut 71 9  32 9 1
ehdrive 42 11  45 9 1
eledisolat 344 9  34 9 1
eldrive 55 9  54 9 1
vcc1inside 23 1 DC 5
vclamp 80 9 DC 2
vfaultreset 92 9 DC 1
vcc2internal 130 9 DC 30
vdesat 30 9 DC  7
vuvlo 37 9 DC  11
vfault 212 1 DC 3
idesat 16 14 DC 250e-6
dclamp 9 10 dmod
dmosl 9 11 dmod
ddrive3 47 46 dmod
ddrive2 49 47 dmod
ddrive1 11 49 dmod
qfault 3 25 1  npnmod
qdrive3 13 46 47  NPNMOD
qdrive2 13 47 49  NPNMOD
qdrive1 13 49 48  NPNMOD
giledfault 9 15  32 9 500e-6
mclamp 10 84 9 9 nmosmod L=1e-6 W=15e-3
mlogic2 14 36 16 9 nmosmod L=1e-6 W=100e-6
mlogic 11 71 9 9 nmosmod L=1e-6 W=27e-6
mdrive 11 555 9 9 nmosmod L=50e-9 W=500e-6
chigh 13 11 30e-12
clgate 555 9 1e-12
cfault 211 1 1e-9
clow 11 9 2e-12
chgate 46 11 120e-12
creset 344 91 1e-9
rfaultbase 25 24 15e3
ricc1 2 1 100e3
rcathode 5 8 1e-6
ruvlo2 38 377 50e3
rgnd2 9 12 1e-6
rfault 210 211 1e3
ranode 7 6 1e-6
rreset 91 9 1e3
rhgate 42 46 1e3
rlgate 55 555 1e3
rgnd 4 1 1e-6
ruvlo 377 37 1e3
rehdrive 48 11 1
rdesatshut2 71 9 1e3
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends ACPL332J

.subckt icc 1 2
r2 3 1 600
r1 6 4 100
qnpn2 4 3 1  NPNMOD
qnpn1 5 4 3  NPNMOD
qpnp2 5 5 2  PNPMOD
qpnp1 6 5 2  PNPMOD
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends icc

.subckt or3 1 2 3 4 5 6
r2 2 6 10e3
r1 2 7 10e3
m4 6 7 1 1 nmosswitch L=1e-6 W=100e-6
m3 7 5 1 1 nmosswitch L=1e-6 W=100e-6
m2 7 3 1 1 nmosswitch L=1e-6 W=100e-6
m1 7 4 1 1 nmosswitch L=1e-6 W=100e-6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends or3

.subckt and3 1 2 3 4 5 6
r2 2 6 10e3
r1 2 7 10e3
m4 6 7 1 1 nmosswitch L=1e-6 W=100e-6
m3 9 5 1 1 nmosswitch L=1e-6 W=100e-6
m2 8 4 9 1 nmosswitch L=1e-6 W=100e-6
m1 7 3 8 1 nmosswitch L=1e-6 W=100e-6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends and3

.subckt limitl 1 2 3
elimit 4 1  2 7 10
vnegativ 6 1 DC -10
vthreshold 7 1 DC  8
vpositive 5 1 DC 10
dnega 6 3 dmod
dposi 3 5 dmod
r2 4 3 1e3
r1 2 7 10e6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends limitl

.subckt limit 1 2 3
elimit 4 1  2  7 10
vnegativ 6 1 DC -10
vthreshold 7 1 DC 8
vpositive 5 1 DC 10
dnega 6 3 dmod
dposi 3 5 dmod
r2 4 3 1e3
r1 2 7 1e6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends limit

.subckt and4 1 2 3 4 5 6 7
r2 2 7 10e3
r1 2 8 10e3
m1m4 7 8 1 1 nmosswitch L=1e-6 W=100e-6
m4 11 6 1 1 nmosswitch L=1e-6 W=100e-6
m3 10 5 11 1 nmosswitch L=1e-6 W=100e-6
m2 9 4 10 1 nmosswitch L=1e-6 W=100e-6
m1 8 3 9 1 nmosswitch L=1e-6 W=100e-6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends and4

.subckt or2 1 2 3 4 5
m3 5 6 1 1 nmosswitch L=1e-6 W=100e-6
m2 6 3 1 1 nmosswitch L=1e-6 W=100e-6
m1 6 4 1 1 nmosswitch L=1e-6 W=100e-6
r2 2 5 10e3
r1 2 6 10e3
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends or2

.subckt led 1 3 4 5
gband 1 3  9 1 1
fphoto 1 9  vsense  1
egain 7 4  6 4 1
cdelay 9 1 70e-9
cband 3 1 10e-12
ithre 3 1 DC  1e-3
vsense 8 4 DC  0
dled 6 4 lednor
doptic 7 8 lednorc
rband 3 1 2e3
rthermo 9 1 1
rled 5 6 1
.MODEL  LEDNOR D IS=5E-16 N=2 XTI=3 EG=2.1 BV=5 IBV=10u
+  CJO=60p VJ=.75 M=.3333 FC=.5 TT=20n
.MODEL LEDNORC D IS=5E-16 N=2 XTI=3 EG=2.1 BV=5 IBV=10u
+  VJ=.75 M=.3333 FC=.5
.ends led

.subckt inverter 1 2 3 4
m0 4 3 1 1 nmosswitch L=1e-6 W=100e-6
r1 2 4 10e3
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends inverter

.subckt and2 1 2 3 4 5
m3 5 6 1 1 nmosswitch L=1e-6 W=100e-6
m2 7 4 1 1 nmosswitch L=1e-6 W=100e-6
m1 6 3 7 1 nmosswitch L=1e-6 W=100e-6
r2 2 5 10e3
r1 2 6 10e3
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends and2

.subckt r_s 1 2 3 4 5
m4 5 3 1 1 nmosswitch L=1e-6 W=100e-6
m3 5 6 1 1 nmosswitch L=1e-6 W=100e-6
m2 6 5 1 1 nmosswitch L=1e-6 W=100e-6
m1 6 4 1 1 nmosswitch L=1e-6 W=100e-6
rl 5 1 50e3
r1 2 6 10e3
r2 2 5 10e3
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends r_s

.subckt comparator 1 2 3 4 5
mcopa 5 6 1 1 nmosswitch L=1e-6 W=100e-6
egain 6 1  3 4 1e3
ro 5 2 10e3
rgate 6 1 10e3
r1n 3 4 1e6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+1.2   RS=0.5  LAMBDA=0)
.MODEL pmosmod pmos (vto=-0.2 )
.MODEL npnmod  npn bf=11
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends comparator

 

  • oldmouldy

    If the simulation starts the issue will, most likely, not be with the model or the way that you have configured the libraries, it may well be down to your application circuit or simulation parameters. See the section in the pspug.pdf, in the doc\pspug directory of the installation, Appendix B covers handling Convergence related issues when simulating.

    The "Vendor App guy" may well have a different SPICE tool but the nuance of simulation settings are more likely to be what sets things apart.

  • rockiesmike

    OK, will review appendix B on convergence and my simulation.  But do you have any comments is the spice model with the subckt created correctly?  If I could find an example of this it would help in letting me know at least I did that correctly.  Only documenntation on implementing subcircuits I found in the pspice user guide was Hieracrchical Design and subcircuit with the X subcircuit general form. 

    X name [node] subcircuit-name

  • rockiesmike

    In the vendor rep's netlist there were two line entries that I web searched and I believe has to do with the spice tool used.  Node 204 was the common ground.  Rgnd is referenced in the model.  Do I need something in my pspice circuit to tied to Vgnd and Rgnd?

    Vgnd 204 0 dc 0V
    Rgnd 204 0 100MEG

     

  • rockiesmike

    LIFE IS GOOD!  The convergent problem was corrected with the simulation configuration.  Enable GMIN and set it to 1E-9, changed the ITL 1, 2 & 4 to their max values 400, 100 and 500.  The simulation took a long time, reducing the simulation peroid would help.  What a way to learn this tool, not a fun process but worth the result (I think).

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