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Invisible power pins on opamp fail to connect to global net

John Davies
I have a library of opamps that I use for teaching, which includes capture symbols and pspice models. All worked well with release 16.2 but two problems have arisen in 16.3. The first is that I hide the power pins using the "Pin Visible" check box in the Pin Properties dialog box. Power is provided through power symbols called V+ and V- somewhere in the circuit, which create global nets. This no longer works in 16.3. Now I have to make the pin visible using the same dialog box. It is not necessary to draw a wire to the pin, just to make it visible; it then connects to the global net. I am not sure whether this is part of the enhanced power pins features in release 16.3 or whether it is a bug.

  • In 16.3 - there are enhancements for localization of global power on page or schematic hierarchy level. However I do not think that is your issue here.

     I suggest the following steps -

    a) Please check that you have the latest ISR installed from http://downloads.cadence.com . Current version is S025.

    b) If you still see the problem - open the design and in the TCL shell in Capture - execute the following TCL commands

    package require capDesignUtil;

    ::capDesignUtil::reevaluateAllPagesOfOpenDesigns

    This will rebuild the connectivity for the open design c) If the problem still persists -- please open the issue at customer support with an example of library part and sample design. Connectivity issues usually get a higher priority by R&D. 

     

  • From a quick test with 16.2.s003 Jul 8 2009, this did not work in 16.2 either, global power nets are created and connected for the PCB netlist formats but not for the PSpice netlist. Equally, if you create a PCB netlist, there will be no V+ / V- nets, apart from the device pins since the PSpiceOnly property will get the sources removed from a PCB netlist.

  • The oldest version that I have running is 10.5, this shows the same behaviour, if the V+ / V- pins are invisible, the connections are not made and the netlist fails. It is possible that this might have worked at some point but it seems like this has not worked for quite some time.

  • Checked on 16.3 ISR S025 - you can assign the invisible pins connections to a global net. These get exported by the global name  - the best place to check this is in pin section in property editor.

     PSpice netlister will require these nets to be connected to a global net. You can connect a global symbol V+ with lets say +12V global symbol up in hierarchy or another page. Basically - The connection assignment for V+ must exist which assigns V+ name with another global flatnet name.

     

  • I'm grateful to oldmouldy for clarifying the position. I hadn't appreciated that the netlisters for pspice and PCB editor have such different behaviour (and I may have been thinking of Layout in the past). I have now revised my library so that the power pins are all visible and the symbols work in both applications.
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