Packaging Error

Can you add more detail ? What schematic software ? What errors ?

 I am using Allegro PCB Design HDL andhave a very simple circuit. I have no schematic errors but when I try to package it for the layout, it hangs and gives me errors.

 can you post log data from export physical process?

we can see what the problem is from there..

 Can't find that. It gives me no log file to view! (It takes forever it seems to even get this far!)

But when  I try to import logic file I get this:

Cadence Design Systems, Inc. netrev 16.2 Tue Mar 15 08:36:26 2011
(C) Copyright 2002 Cadence Design Systems, Inc.

------ Directives ------

RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'H:/Cadence/EU_Power_Board_Project/worklib';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'H:/Cadence/EU_Power_Board_Project/worklib/design_ce_eu_power_board/physical/design_ce_eu_power_board.brd';
NEW_BOARD_NAME 'H:/Cadence/EU_Power_Board_Project/worklib/design_ce_eu_power_board/physical/design_ce_eu_power_board.brd';

CmdLine: netrev -$ -i H:/Cadence/EU_Power_Board_Project/worklib -l -u -y 1 -o H:/Cadence/EU_Power_Board_Project/worklib/design_ce_eu_power_board/physical/#Taaaaaa02704.tmp

------ Preparing to read pst files ------


#1   ERROR(24) File not found
     Packager files not found

#2   ERROR(102) Run stopped because errors were detected

netrev run on Mar 15 8:36:26 2011

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

  2 errors detected
 No oversight detected
 No warning detected

cpu time      0:02:37
elapsed time  0:00:00

When you package the design using File -Export - Physical for now uncheck Update PCB Editor Board. Then click on OK. Does the packager complete sucessfully ? If so open PCB Editor and use File - Import - Logic, Select HDL as the input type and browse to where the packager files are (it uses three and if you use the default naming conventions will be H:/Cadence/EU_Power_Board_Project/worklib/folder name/packaged (where folder name is the Design name). Once set PCB Editor should find your packaged files and continue with the import. That is the current error shown above.