Stats

  • Locked Locked
  • Replies 2
  • Subscribers 166
  • Views 12851
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

FPGA PCB design considerations

Lambros

Hi,

     I am currently working on a data acquisition system that includes an ADC, a SRAM memory chip and an FPGA. The main idea here is to sample the waveforms with the ADC, feed the data to the memory chip, then use the FPGA and some USB  device to send the data from the memory chip to the FPGA and then to a PC for further processing. The ADC chip uses LVDS but the SRAM uses CMOS so I also have to use a translation IC between those to. I have two problems that have to do with the PCB design:

1) At first I want to send the digital data at 200 MHz from the ADC to SRAM. When this process is done, the data will be transferred at a much slower speed from the SRAM to the FPGA. The question is: Can I hardwire the SRAM data bus both to the ADC and the FPGA or this could cause damage (e.g. due to signal reflections) to any of the two devices when the SRAM communicates with the other?  The translator I use has an Enable/Disable function which I can use to isolate the ADC when the SRAM sends the data to the FPGA, while I can use some tristate option for the FPGA I/O pins for the opposite situation.

 2) Because LVDS is a source synchronous interface, the ADC also provides a synchronizing clock along with the data (also LVDS). In order to synchronize the data with the SRAM addressing I need to feed that clock to the FPGA. Is it possible to create some internal signal delay inside the FPGA in order to compensate for the delay inserted by the translation device (according to the datasheet, 2.6 ns), or is such compensation unachievable? 

 

thanks in advance,

Lambros Gavriilides

  •  Lambros,

    Many questions. Is this a student project?

    In answer to your question on connecting three devices to the SDRAM bus. 

    It is unlikely that there will be enough energy in the reflected waveforms to damage any of the components. However, this does not mean that your system will work. I suggest you use the SigXP tool to simulate your proposed layout and to constrain the design. Think carefully about termination resistors. With just three components on the bus, it will be difficult to wire anything other than a fly by topology.

     You will need to look carefully at that level shifter. Does it act like a passive component in series with your transmission line, or does it act to break the transmission line in to two chunks. Either:

    ADC - passive - SRAM - FPGA

    or

    ADC - levelshifter

    & 

    Levelshifter - SRAM - FPGA

     

    Tristating the level shifter or the FPGA, doesn't  disconnect the copper traces, and therefore you should simulate to see what the reflection looks like.

     

    Your second question. Yes, that is possible through timing constraints in the FPGA synthesis tool. It's not good practise to create an asynchronous delay though. Such delays vary with temperature, voltage, process etc. They also consume vast amounts of FPGA logic. Consider using the FPGA clock to generate a registered delay. You may be better served looking at a different solution, for example, how about clocking out the SRAM address on the other edge of the ADC clock? So if ADC presents data on the positive clock edge, then you change address on the negative.

     

    I hope these pointers help.

  •  Hi Mike and thank you for your reply.This, indeed, is a student project. As for the first question I have chosen to drive the data from the ADC to the FPGA at first and then to the memory modules. Thank you for your reply anyways. As for the second question, what I am planning to do is receive the data and their clock inside the FPGA and then drive them directly to the memory chips, using that data clock  to both clock and address the devices.I will follow your advice and clock out the SRAM on the falling edge, compensating for any signal delays.

     

    thank you,

    Lambros

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.