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Newbie DDR2 PCB design

komikumi

 I'm routing a PCB with 1 CPU and 2 DDR2 SDRAM. Follow some doccuments from the Inthernet I created 4 group : DATA, ADDRESS, CONTROL and SCLK and also did lenght matching for 4 groups above. My question is: how will I set the constrain about the length of the one of above groups to each other ?

SCLK >  ADDRESS > CONTROL > DATA or

SCLK = ADDRESS = CONTROL = DATA ?

In PCB editor, there are two option for the unit of the delta value (propagation delay), because the speed of the the current between the TOP layers and MID layers are difference but why many peoples use the unit in [mm] (or mil) instead using the unit in [ns] ?

Hope sombody give me some advice about this problem.

Thank you.

 

 

 

 

  • Mike Veal

     There have been lots of conference papers about this. You can get them by clicking the "resource library" link at the top of this page and searching.

     

    This was mine from a few years ago:

    http://www.cadence.com/rl/Resources/conference_papers/stp_cdnliveemea07_ddrconstraints_veal.pdf

    In it I show what needs to be constrained and how the constraints are inter-related. I suggest a wiring scheme to make constraints easier. If you have questions on this presentation, I'll do my best to help.

     

    These DDR papers are good:

     For DDR2/3:

    http://www.cadence.com/rl/Resources/conference_papers/8.4Presentation.pdf

    For DDR3:

    http://www.cadence.com/rl/Resources/conference_papers/stp_designcon08_DDR3Altera.pdf

  • komikumi
    Dear Mr Mike Veal, many thanks for your usefull links, I'll read them. Best regards
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