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Question: how to reuse the layer shapes and traces information of the module

wustlgao

Hi, guys

I am trying to combine to the layouts of two projects (both are small boarsd with the same constraints setting) together. Now I am following the method in Cadence "Design entry HDL reuse" tutorial to first create sub-circuit and module, then backannotate the sub-circuit schematic and create the symbol. Next in the top level schematic add this symbol then export to layout by using "force subcircuit" to add the module. 

However, in the generated top level layout file. The shapes and traces show up, but all the symbols of the module are needed to be placed again. And it seems the shapes and traces don't "remember" which net they belong to....

I think the problem could be when doing the back annotation, the information of the shape and traces are not backannotated to the schematic. But I didn't find anything useful to help solve that. But I tried to open the module file using the PCB editor, it has all the things in there!

Does anyone know how to reuse the whole module without losing the shape and traces information? It's really annoying to place all the components once again and re-do the routing.

Thank you in advance!:)

Shengkui

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  • wustlgao

     I tried, but no components had been placed.

    The way we are using right now is generate a subdrawing for one subdesign, then import it to top design. But since it lost all the information, we need to copy the schematic of this subdesign into the top schematic, and use the "ResDef" function in the PCB editor to assign the ResDef information to the components in the subdrawing, also assign the net name (gnd, vcc) to the correponding layer shapes. Then the subdrawing layout can "realize" all the traces and pins information automatically and pass the DRC check.

     It's a little time-consuming, but not wastes that much.

    Shengkui

     

Reply
  • wustlgao

     I tried, but no components had been placed.

    The way we are using right now is generate a subdrawing for one subdesign, then import it to top design. But since it lost all the information, we need to copy the schematic of this subdesign into the top schematic, and use the "ResDef" function in the PCB editor to assign the ResDef information to the components in the subdrawing, also assign the net name (gnd, vcc) to the correponding layer shapes. Then the subdrawing layout can "realize" all the traces and pins information automatically and pass the DRC check.

     It's a little time-consuming, but not wastes that much.

    Shengkui

     

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