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Orcad to Allegro netlist: Net names in a hierarchical design

Hi,

How can I change the way my hierarchical net names are constructed?

When I netlist I get my net name with the block name affixed to the end with underscore separator: <net_name>_<block_name>

i.e for net = DDR_DQ0, inside block named FPGA, I get DDR_DQ0_FPGA.

I would like the block name to be a prefix... FPGA_DDR_DQ0.

Can anyone tell me how I can control this?

Thanks

oldmouldy over 13 years ago

The value can only be appended. Either an ID, or the block name can be appended, this will be appended either when there is a collision, or always. Launch the Extended Preferences Setup / Designs and Libraries / Net Naming Options from Accessories>Cadence Tcl/Tk Utilities>Utilities...
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archive over 13 years ago

Thanks very much for your help.
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