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Confused about copper pour spacing to hole

DrLightning

With a new PCB manufacturer, some constraints have changed and I'm trying to get them working correctly.  But I don't think my constraints are working correctly.  I'm using OrCAD PCB Editor version 16.3 [16.3 p006 (v16-3-85F)(11/10/2009) i86].

I have a via named "Via18cir_fin8_tinted" that has an 18mil diameter pad with an 8mil hole (finished size).  On my internal GND layer I have a copper pour (a shape for net "GND").  When the via is for a different net than GND, the GND layer shape shows an opening in it around the via, just as it should.  But when I measure things, they don't add up properly.

In the constraint manager, I have a whole bunch of 4mil spacing defined, including "Shape To Thru Via".  When I set my grid down to 0.01mil and measure by positioning my cursor and reading the X,Y coordinates at the bottom right corner of the screen, I am able to confirm that the via is 18mil diameter.  When I do the same for the opening in the GND pour, I measure 26.04mil.  While I would have expected to measure 26.00mil, this 26.04mil is acceptable.  It's 8.04 mil greater than the via diameter, and so the spacing from the via to the edge of the GND pour must be 4.02mil, which satisfies the 4mil "Shape to Thru Via" spacing constraint.

However, this via has an 8mil hole.  The 26.04ml opening relative to the 8mil hole is only a 9.02mil space.  This VIOLATES the 10mil spacing constraint that I have defined for "Hole to Shape".  This constraint used to be 8mil, but I changed it as a part of today's updates to be 10mil.  After first making this change, I ran Display / Status / Update [Shapes] To Smooth, and the appearance of the pour changed significantly as I would suspect, even creating some islands.  So I would have thought my 8 to 10 mil change happened.  But as I said, when I try to measure, it doesn't seem correct to me.

What's up?

I inspected further.  The older board has the same 26.04mil opening around the 18mil via with 8mil hole.  Regarding the islands that developed when I changed the constraints, it appears that the spacing from the 2-row header pads to the pour  (the case in point) didn't change.  Perhaps only the thickness of the pour squeezing between the pads changed, not the spacing.  So how do I make the spacing on this pour change?

  • jch teyssier

     Maybe it is not that, but there were an undocumented thing in older versions (maybe it s the same for 16.3 and 16.5?).

    If a via is a testpoint, then the constraint used is for test point, EVEN IF A GREATER SPACING VALUE is defined for this net for vias.

    Exemple:

    via/shape defined to 25 mils

    shape/testvia defined to 10 mils

    The value used is 25 if via is not defined as a testpoint; 10 if via is defined as a testpoint.

     

    Maybe your problem is here?

     

    Jean-Charles

  • DrLightning

    What is meant by "via" here, the pad or the hole in the via? To date, I'm only setting constraints relative to holes, not vias...

    (and it's NOT a testpoint) 

  • steve

    The Hole to rules are only applied when the pad has been supressed or not used (i.e. the pad is smaller than the hole for a mechanical hole). So you need to set Via to Shape to get accurate results. Also check Global Shape Params to make sure you specify DRC rather than Thermal anti for thru pins, vias and smd pins. This then means the tools will use the spacing rules in CM rather than the thermal/anti pad defined in pad designer.

    You are also running the base release of the software. I would get the latest hotfix avaliable from the downloads.cadence.com or the local VAR if you bought it that way.

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