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  3. unable to backannotate the design

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unable to backannotate the design

davidsun
davidsun over 13 years ago

Hello

I searched Cadence forums, I found a post by DanielAmir

 Greetings,

 I am experiencing a problem while I am trying to backannotate the swapped pins to the schematic. It keeps complaining:

"Unable to backannotate the changes to design file "\ABCD\.DSN" because the original design file used to create the board has a different name "ABCD.DSN". Choose the correct design file and backannotate again."

But I have used the same file to create the PCB and I don't have  any idea where those "\"s are comming from. Does any one have any idea?

Thanks,

Daniel 

 I encounted same problem. I am using orcad 16.2, capture and PCB editor. the schematic name I used as "TOL_1234.sch, Rev01, development board.dsn"

and the error message is

"Unable to backannotate the changes to design file '\TOL_1234\.DSN' because the original design file used to create the board has a different name 'TOL_1234.DSN'. Choose the correct design file and backannotate again."

I have tried to change the name to "TOL_1234.DSN" but it didn't work. I guess the problem is the period in the file name. anyone know how to work this around.

appreciate you help, thanks,

David 

 

 

 

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  • oldmouldy
    oldmouldy over 13 years ago
    16.2 is probably going to have a pretty low tolerance for your design name, take a copy of the files and simplify things to be named, "something like" "Design.dsn" and create all the files again, you will need to create the netlist and try to load this into the BRD file that you have and then rework the board data as necessary to get the physical layout back.
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  • davidsun
    davidsun over 13 years ago

    thank you very much for replying my post, I followed your suggestion and did several test. I found that the problem is not the file name. if I intentionalyl delete a part in schematic, and then redo the back annotate, then the Cadence will generate the same complain. here is my test sequence

    1. Capture, create netlist.

    2. import to PCB Editor.

    3. back annotate in Capture. it works.  

    4. delect one part in the schematic. save design and redo back annotate. then it report the problem. 

     

    I think the error massage is confusing, it want to tell the designer that the schematic has been changed after the netlist been imported to PCB layout. but it seems the file name has problem.

    is my observation correct? 

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