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How to design PCB Footprint for SMD Transistor

Gopintj1

Hi friends,

      As i am very new to PCB designing using CADENCE Allegro, i would like to know how to design foot print for SMD Transistor which is shown here. As per my knowledge, i have created foot print for micro controlles(QFP) whose pin numbers are same in four faces. But, here, we have only one pin in one direction and two pins in opposite direction.

     Please guide me how to design foot print for this. 

SMD Transistor

  • I would suggest starting off with pulling the datasheet and creating the footprint accordingly.  

    It should tell you how to assign the pin number pad size etc.

  • Hello, that appears to be a SOT-23 Package, so you could create it from scratch but if you are looking for an easier method then have a look in the allegro pcb footprint library for the following symbol "SOT23.DRA" Typically the symbol library is located under your install folder

    C:\Cadence\SPB_16.5\share\pcb\pcb_lib\symbols

    Load up the symbol in the editor and have a look. Turn on all the color layers so you can see all the detail of the symbol. If you hover your mouse over part of the symbol it will tell you what the object is and what class it is a part of. Make sure you turn on all objects such as lines pins shapes etc in the find filter dialog box as a first step.

    Make some notes of the symbol structure or draw a sketch of it's layer structure. In general your silkscreen top layer and place bound top layer are contained in the "Package Geometry", Your Padstacks would be under "Stack up" Reference Dez would be under "Components"

    Be aware that some symbols in the symbol library do not have a silkscreen top layer so be mindfull of that. The sot23.dra symbol would be an example of that : )

    Thanks Scott 

  • Hello - I would also like to make you aware of an excellent, free resource that is available through www.pcblibraries.com.  This website provides a wealth of information regarding pcb libraries, footprint creation, etc.  It has the additional benefit of being endorsed by the IPC so the advice and knowledge available here is advice and knowledge that is being used throughout the EDA industry.  Hope you find it helpful.

  • Thanks ScottCad. Now i could design footprint for this component. Well, I get struck while i come to design footprint for Crystal Oscillator where i have to merge one SMD pad with a via. This pad is connected to ground plane to take out the heat produced by the crystal oscillator. Is it possible to create this kind of pad using cadence allegro 15.2? Please give me some idea about this.

     Also, in some circuits, i found solder lead is poured as like copper pour which we often use to short ground plane. Could you please explain me how to do that?

     

  • Besides pulling the appropriate datasheet, you might also consult the IPC-782, which shows all sorts of footprints. As you will find out, footprints can (will) differ between manufacturers. The IPC document will give you a great starting point. This is a good time to build your library of pad stacks as well. Give them a common sense name(e.g 25X60) Ron Scott
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