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Avago HPCL-3120

Martins

Hi,

 I need to convert Avago HPCL-3120 to Capture and Pspice. Not usually a big problem but this time it not as usual.

* HCPL-3120 SPICE Macromodel
* (also applies to HCPL-J312)
* Rev. A
* 09/07
* ZFC
*
* This is the behavioural model for the above-mentioned part number.
* It is valid for functional simulation over the range specified below.
* (over recommended operating conditions as specified in the datasheet)
*
* Macromodels provided by Avago Technologies are not warranted
* as fully representing all of the specifications and operating
* characteristics of the product.
*
* Macromodels are useful for evaluating product performance but they
* cannot model exact device performance under all conditions, nor are
* they intended to replace breadboarding for final verification.
*
* Copyright 2007 Avago Technologies Limited. All Rights Reserved
********************************************************************************
*
*               pin1     to    pin8
*                 |             |
.subckt HCPL_3120 1 2 3 4 5 6 7 8
q2icc 163 84 8  pnpmod
q1icc 84 84 8  pnpmod
xled 5 10 3 2 led
xlimitl 5 10 50 limitl
ehdrive 42 7  40 5 1
eldrive 51 5  50 5 -1
xhlimit 5 10 40 limit
vuvlo 20 5 DC 12
vccinside 22 5 DC 30
dmosl 5 7 dmod
ddrive3 47 46 dmod
ddrive2 49 47 dmod
ddrive1 7 49 dmod
q4icc 122 124 5  npnmod
q3icc 84 122 124  npnmod
qdrive3 8 46 47  NPNMOD
qdrive2 8 47 49  NPNMOD
qdrive1 8 49 48  NPNMOD
xuvlo 5 22 8 21 23 comparator
muvlo 10 24 5 5 nmosswitch L=1e-6 W=100e-6
mdrive 7 52 5 5 nmosmod L=1e-6 W=10e-3
cuvlo 24 5 20e-12
chigh 8 7 1e-12
clgate 52 5 1e-12
clow 7 5 1e-12
chgate 46 7 300e-12
rshort67  6 7  0.0001
ruvlo2 23 21 40e3
r2icc 124 5 600
ruvlo3 23 24 1e3
r1icc 163 122 1e3
rhgate 42 46 1e3
rlgate 51 52 1e3
ruvlo 21 20 1e3
rehdrive 48 7 1.4

.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+0.5   RS=0.9  LAMBDA=0)
.MODEL npnmod  npn bf=16
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends HCPL_3120

.subckt led 1 3 4 5
gband 1 3  9 1 1
fphoto 1 9  vsense  1
egain 7 4  6 4 1
cband 3 1 140e-12
ithre 3 1 DC 500e-6
vsense 8 4 DC 0
dled 6 4 lednor
doptic 7 8 lednorc
rband 3 1 1e3 TC1=2e-3
rthermo 9 1 1 TC1=-1.5e-3
rled 5 6 1
.MODEL LEDNOR D IS=5E-16 N=2 XTI=3 EG=2.1 BV=5 IBV=10u
+  CJO=60p VJ=.75 M=.3333 FC=.5 TT=20n
.MODEL LEDNORC D IS=5E-16 N=2 XTI=3 EG=2.1 BV=5 IBV=10u
+  VJ=.75 M=.3333 FC=.5
.ends led

.subckt limitl 1 2 3
elimit 4 1  2 7 10
vnegativ 6 1 DC -12
vthreshold 7 1 DC 2
vpositive 5 1 DC  12
dnega 6 3 dmod
dposi 3 5 dmod
r2 4 3 1e3
r1 2 7 10e6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+0.5   RS=0.9  LAMBDA=0)
.MODEL npnmod  npn bf=16
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends limitl

.subckt limit 1 2 3
elimit 4 1  2 7 10
vnegativ 6 1 DC -10
vthreshold 7 1 DC 2
vpositive 5 1 DC 10
dnega 6 3 dmod
dposi 3 5 dmod
r2 4 3 1e3
r1 2 7 1e6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+0.5   RS=0.9  LAMBDA=0)
.MODEL npnmod  npn bf=16
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends limit

.subckt comparator 1 2 3 4 5
mcopa 5 6 1 1 nmosswitch L=1e-6 W=100e-6
egain 6 1  3 4 1e3
ro 5 2 10e3
rgate 6 1 10e3
r1n 3 4 1e6
.MODEL nmosswitch nmos (vto=+0.7)
.MODEL nmosmod nmos (vto=+0.5   RS=0.9  LAMBDA=0)
.MODEL npnmod  npn bf=16
.MODEL pnpmod  pnp bf=100
.MODEL dmod D IS=2.22P CJO=1P VJ=.376 M=.139 N=1.07
.ends comparator

========================================

When I import it goes until ".ends HCPL_3120". It seems to be a multi-whatever part.

When I import through IBIS translator (jut guessing) it creates several parts. Then I retouch HCPL_3120 in Captue->File->OpenLibrary ...I place it in circuit.

****** The line above is wrong, wat I was trying was file open directly to the *.txt Avago file ************

Well, pins 1 and 4 are NC. If I do not connect them, I get NET0075 unconnected pin. If I connect a ground (what should I?) I get in PSpice "Incorrect Number of Interface Nodes". (Just is case, I connect pins 6 and 7 together, these are the same output (parallel)).

This is quite annoying. I don't have a clue about this.

Any help is appreciated.
Martins

  • Since pins 1 and 4 are unused and unmodeled, it would be better if the model had only the 6 active pins and you ignored the unused pins. PSpice has a FLOAT pin property which takes care of this, FLOAT=UNMODELED pins are not added to the netlist and are not part of the template. Anyway, as things stand with the 8 nodes on the Model interface, the FLOAT for Pins 1 and 4 of the schematic part will need to be set to RtoGND, and then wired together in the schematic. There is also an issue with the TC1 parameters for Rband and Rthermo, the documented PSpice syntax is TC=TC1[,TC2], so the parameter should be TC=<value>, not TC1=<value>. I have attached a trivial test case and modified LIB file that works with the 8-node model.
    OptoCoupler-2013-03-11T21-21.zip

  • Thank you for your answer. It worked fine.

    It is surprising that Avago has since long ago a faulty simulation file. Some month ago I complaint to them that something wasn't right but their answered that everything was OK.

    Thanks
    Martins

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