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DDR2 and DDR3 connections

akael

 Hi, I'm quite confused about schematic with DDR2 or DDR3 memory, I've checked several design, and some design have the pin D0 of the chip memory connected to net MDQ0,D1 connected to MDQ1 ( the other pins have the same logic, with the respective number bit) , so i can understand it , BUT OTHER DESIGN ARE VERY DIFFERENT , just for example the pin D0 of the chip memory is connected to MDQ5, D1 connected to MDQ7 ..., it's another technique, there is logic for this? pls i hope someone can help me.

  • tltoth

     Data lines within the same byte-lane can be swapped to ease the routing

  • akael

     Thanks for your answerd , i think i couldn't find a information because of I didn't use the keyword " byte-lane can be swapped", now i found it.

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