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[Help] PADS layout to Allegro PCB translation

momo1982

Hi all,

First, thanks for the time of you on this post.

I have a 8-layer PADS PCB layout designed by other people, which you can see from the attached Figure 1. What I want to do now is to extract the footprints of components in the PADS board layout to Allegro, so I don't need to redraw the footprint of some component. I have done some homework on the procedure, which is explained below, but still can't get it done.

The version of the PADS software is 9.5. The Allegro version is 16.6.

1: First, export the PADS PCB layout into .sci format. The settings is in attached Figure 2. Is it correct?

2: Copy the default pads_in.ini file to my directory. The contents of this file is listed in Figure 3. But I don't know how to modify it based on my case.

3: Launch in Allegro that File-->Import-->CAD Translator-->PADS, choose the .asc and .ini file, and run Translate.

I get some errors here, which is listed below:

Using translator version @(#)$CDS: pads_in.exe v16-6-112X 3/11/2013 Copyr 2013 CADENCE DESIGN SYSTEMS.

Reading PADS ASCII file header.

PARSE ERROR: Unrecognized format in header line of input file.

Line 1: !PADS-POWERPCB-V9.5-BASIC! DESIGN DATABASE ASCII FILE 1.0

ERROR: Finished with errors.

 

 

 

  •  I also include here the beginning part of .asc file.

     

    !PADS-POWERPCB-V9.5-BASIC! DESIGN DATABASE ASCII FILE 1.0

    *PARTDECAL* ITEMS

    *REMARK* NAME UNITS ORIX ORIY PIECES TERMINALS STACKS TEXT LABELS

    *REMARK* PIECETYPE CORNERS WIDTHHGHT LINESTYLE LEVEL [RESTRICTIONS]

    *REMARK* PIECETYPE CORNERS WIDTH LINESTYLE LEVEL [PINNUM]

    *REMARK* XLOC YLOC BEGINANGLE DELTAANGLE

    *REMARK* XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST

    *REMARK* VISIBLE XLOC YLOC ORI LEVEL HEIGTH WIDTH MIRRORED HJUST VJUST RIGHTREADING

    *REMARK* FONTSTYLE FONTFACE

    *REMARK* T XLOC YLOC NMXLOC NMYLOC PINNUMBER

    *REMARK* PAD PIN STACKLINES

    *REMARK* LEVEL SIZE SHAPE IDIA [CORNERRADIUS] [DRILL [PLATED]]

    *REMARK* LEVEL SIZE SHAPE FINORI FINLENGTH FINOFFSET [CORNERRADIUS] [DRILL [PLATED]]

    0402 I 38100000 38100000 2 2 1 0 2

    OPEN 4 381000 0 0

    -476250 1143000

    -2209800 1143000

    -2209800 -1143000

     

     

    Anybody could give me some help?

     

    Thanks so much~~

     

     

  •  Problem Solved by myself...

     Choose PADS Layout V2007 when exporting .asc file, no matter what your PADS version is. No need to modify .ini file.

  • Only thing we noticed is the translated symbols left us without DFA or placement DRC boundaries.

    The translator makes no attempt to reuse existing padstacks.  Just builds new padstacks with a serial number each time.

    Used our library automation to generate a second library with footprint names matching what we had in PADS (we didn't follow IPC naming convention back then).

     

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