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PSpice Model for a 4017 Decade Counter?

I found the following model code for a CD4017B decade counter, but it doesn't work. I'm getting an error as seen in the attachment. The model code I found is:

*---------
* CD4017B CMOS COUNTER/DIVIDER
*
* CMOS INTEGRATED CIRCUITS DATABOOK, 1983, RCA SOLID STATE DIVISION
* NH 9/8/92      REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES
*
.SUBCKT CD4017B CLK_I CLKINHIBIT_I RESET_I O0_O O1_O O2_O O3_O O4_O O5_O O6_O
+               O7_O O8_O O9_O CARRYOUT_O
+ OPTIONAL: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
*
U17BBUF BUF VDD VSS
+ CLK_I CLK
+ D0_GATE IO_4000B_ST IO_LEVEL={IO_LEVEL}
*
U17BLOG LOGICEXP(13,16) VDD VSS
+ CLK CLKINHIBIT_I RESET_I Q1 Q2 Q3 Q4 Q5 Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR
+ CLKINHIBIT RESET CLOCK O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 CARRYOUT TOQ3 RST
+ D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
+
+ LOGIC:
+
* BUFFERS
+   CLKINHIBIT = { CLKINHIBIT_I }
+   RESET = { RESET_I }
+
* OUTPUT ASSIGNMENTS
+   CLOCK = { ~(~CLK | CLKINHIBIT) }
+   O0 = { Q5BAR & Q1BAR }
+   O1 = { Q1 & Q2BAR }
+   O2 = { Q2 & Q3BAR }
+   O3 = { Q3 & Q4BAR }
+   O4 = { Q4 & Q5BAR }
+   O5 = { Q5 & Q1 }
+   O6 = { Q1BAR & Q2 }
+   O7 = { Q2BAR & Q3 }
+   O8 = { Q3BAR & Q4 }
+   O9 = { Q4BAR & Q5 }
+   CARRYOUT = { Q5BAR }
+   TOQ3 = { ((Q1 & Q2) | (Q2 & Q3)) }
+   RST = { ~RESET }
*
UFF DFF(5) VDD VSS
+ $D_HI RST CLOCK Q5BAR Q1 TOQ3 Q3 Q4 Q1 Q2 Q3 Q4 Q5
+ Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR
+ D0_EFF IO_4000B
*
U17BDLY PINDLY (11,0,4) VDD VSS
+ O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 CARRYOUT
+ CLOCK RESET CLK CLKINHIBIT
+ O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O CARRYOUT_O
+ IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ BOOLEAN:
+   CH_CLOCK = { CHANGED_LH(CLOCK,0) }
+   CH_RESET = { CHANGED_LH(RESET,0) }
+
+ PINDLY:
+   O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O = {
+     CASE(
+       CH_RESET, DELAY(-1,265NS,530NS),
+       CH_CLOCK, DELAY(-1,325NS,650NS),
+       DELAY(-1,326NS,651NS)                  ;DEFAULT
+       )
+     }
+   CARRYOUT_O = {
+     CASE(
+       CH_RESET, DELAY(-1,265NS,530NS),
+       CH_CLOCK, DELAY(-1,300NS,600NS),
+       DELAY(-1,301NS,601NS)
+       )
+     }
+
+ FREQ:
+   NODE = CLK
+   MAXFREQ = 2.5MEG
+
+ WIDTH:
+   NODE = CLK
+   MIN_HI = 200NS
+   MIN_LO = 200NS
+
+ WIDTH:
+   NODE = RESET
+   MIN_HI = 260NS
+
+ SETUP_HOLD:
+   DATA(1) RESET
+   CLOCK LH = CLK
+   RELEASETIME_HL = 400NS
+
+ SETUP_HOLD:
+   DATA(1) CLKINHIBIT
+   CLOCK LH = CLK
+   SETUPTIME = 230NS
+   WHEN = { RESET!='1 }
*
.ENDS

I think it's missing some lines. Shouldn't there be a line starting with ".model"?

Thanks,

Mike

Sailmike over 11 years ago

My question is about simulating the 4017 decade counter, not making a PCB part. Does anybody know how to correctly simulate a decade counter in PSpice? The model I used for my simulation doesn't work. I found the above model code for the 4017 after an extensive search around the internet and used that to make a custom part for simulation.

Thanks,
Mike
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Alok Tripathi over 11 years ago

4017 model included in this POST refer to IO models and these models are not included, hence this error. Generally this happens if you try to pull out one model from a set of library and all referred models are not included in new library. Here are the missing IO models. You should include these as well in your new library to get rid of above error. .model D0_GATE ugate ().model IO_4000B_ST uio (
+ drvh=1443 drvl=1443
+ AtoD1="AtoD_4000B_ST" AtoD2="AtoD_4000B_ST"
+ AtoD3="AtoD_4000B_ST" AtoD4="AtoD_4000B_ST"
+ DtoA1="DtoA_4000B" DtoA2="DtoA_4000B"
+ DtoA3="DtoA_4000B" DtoA4="DtoA_4000B"
+ tswhl1=7.72ns tswlh1=7.56ns
+ tswhl2=7.86ns tswlh2=7.40ns
+ tswhl3=9.71ns tswlh3=9.41ns
+ tswhl4=9.63ns tswlh4=9.24ns
+ DIGPOWER="CD4000_PWR"
+ ).model IO_4000B uio (
+ drvh=1443 drvl=1443
+ AtoD1="AtoD_4000B" AtoD2="AtoD_4000B_NX"
+ AtoD3="AtoD_4000B" AtoD4="AtoD_4000B_NX"
+ DtoA1="DtoA_4000B" DtoA2="DtoA_4000B"
+ DtoA3="DtoA_4000B" DtoA4="DtoA_4000B"
+ tswhl1=7.72ns tswlh1=7.56ns
+ tswhl2=7.86ns tswlh2=7.40ns
+ tswhl3=9.71ns tswlh3=9.41ns
+ tswhl4=9.63ns tswlh4=9.24ns
+ DIGPOWER="CD4000_PWR"
+ ).model D0_EFF ueff ()One would never get this error if simulation is run using PSpice licensed version (which has complete library set). Installed libraries will include all required models for CD4017B. CD4017B model/part is available in CD4000 library supplied with PSpice installation.
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Sailmike over 11 years ago

Great thank you! I copied and pasted your code, but I'm still doing something wrong. Here's the code as it looks now:

.SUBCKT CD4017B CLK_I CLKINHIBIT_I RESET_I O0_O O1_O O2_O O3_O O4_O O5_O O6_O

+ O7_O O8_O O9_O CARRYOUT_O

+ OPTIONAL: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS

+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0

*

U17BBUF BUF VDD VSS

+ CLK_I CLK

+ D0_GATE IO_4000B_ST IO_LEVEL={IO_LEVEL}

*

U17BLOG LOGICEXP(13,16) VDD VSS

+ CLK CLKINHIBIT_I RESET_I Q1 Q2 Q3 Q4 Q5 Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR

+ CLKINHIBIT RESET CLOCK O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 CARRYOUT TOQ3 RST

+ D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}

+

+ LOGIC:

+

* BUFFERS

+ CLKINHIBIT = { CLKINHIBIT_I }

+ RESET = { RESET_I }

+

* OUTPUT ASSIGNMENTS

+ CLOCK = { ~(~CLK | CLKINHIBIT) }

+ O0 = { Q5BAR & Q1BAR }

+ O1 = { Q1 & Q2BAR }

+ O2 = { Q2 & Q3BAR }

+ O3 = { Q3 & Q4BAR }

+ O4 = { Q4 & Q5BAR }

+ O5 = { Q5 & Q1 }

+ O6 = { Q1BAR & Q2 }

+ O7 = { Q2BAR & Q3 }

+ O8 = { Q3BAR & Q4 }

+ O9 = { Q4BAR & Q5 }

+ CARRYOUT = { Q5BAR }

+ TOQ3 = { ((Q1 & Q2) | (Q2 & Q3)) }

+ RST = { ~RESET }

*

UFF DFF(5) VDD VSS

+ $D_HI RST CLOCK Q5BAR Q1 TOQ3 Q3 Q4 Q1 Q2 Q3 Q4 Q5

+ Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR

+ D0_EFF IO_4000B

*

U17BDLY PINDLY (11,0,4) VDD VSS

+ O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 CARRYOUT

+ CLOCK RESET CLK CLKINHIBIT

+ O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O CARRYOUT_O

+ IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

+

+ BOOLEAN:

+ CH_CLOCK = { CHANGED_LH(CLOCK,0) }

+ CH_RESET = { CHANGED_LH(RESET,0) }

+

+ PINDLY:

+ O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O = {

+ CASE(

+ CH_RESET, DELAY(-1,265NS,530NS),

+ CH_CLOCK, DELAY(-1,325NS,650NS),

+ DELAY(-1,326NS,651NS) ;DEFAULT

+ )

+ }

+ CARRYOUT_O = {

+ CASE(

+ CH_RESET, DELAY(-1,265NS,530NS),

+ CH_CLOCK, DELAY(-1,300NS,600NS),

+ DELAY(-1,301NS,601NS)

+ )

+ }

+

+ FREQ:

+ NODE = CLK

+ MAXFREQ = 2.5MEG

+

+ WIDTH:

+ NODE = CLK

+ MIN_HI = 200NS

+ MIN_LO = 200NS

+

+ WIDTH:

+ NODE = RESET

+ MIN_HI = 260NS

+

+ SETUP_HOLD:

+ DATA(1) RESET

+ CLOCK LH = CLK

+ RELEASETIME_HL = 400NS

+

+ SETUP_HOLD:

+ DATA(1) CLKINHIBIT

+ CLOCK LH = CLK

+ SETUPTIME = 230NS

+ WHEN = { RESET!='1 }

*

.model D0_GATE ugate ().model IO_4000B_ST uio (

+ drvh=1443 drvl=1443

+ AtoD1="AtoD_4000B_ST" AtoD2="AtoD_4000B_ST"

+ AtoD3="AtoD_4000B_ST" AtoD4="AtoD_4000B_ST"

+ DtoA1="DtoA_4000B" DtoA2="DtoA_4000B"

+ DtoA3="DtoA_4000B" DtoA4="DtoA_4000B"

+ tswhl1=7.72ns tswlh1=7.56ns

+ tswhl2=7.86ns tswlh2=7.40ns

+ tswhl3=9.71ns tswlh3=9.41ns

+ tswhl4=9.63ns tswlh4=9.24ns

+ DIGPOWER="CD4000_PWR"

+ ).model IO_4000B uio (

+ drvh=1443 drvl=1443

+ AtoD1="AtoD_4000B" AtoD2="AtoD_4000B_NX"

+ AtoD3="AtoD_4000B" AtoD4="AtoD_4000B_NX"

+ DtoA1="DtoA_4000B" DtoA2="DtoA_4000B"

+ DtoA3="DtoA_4000B" DtoA4="DtoA_4000B"

+ tswhl1=7.72ns tswlh1=7.56ns

+ tswhl2=7.86ns tswlh2=7.40ns

+ tswhl3=9.71ns tswlh3=9.41ns

+ tswhl4=9.63ns tswlh4=9.24ns

+ DIGPOWER="CD4000_PWR"

+ ).model D0_EFF ueff ()

.ENDS

Thank you,
Mike
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Sailmike over 11 years ago

I don't know why my code is double space there. Here's a screenshot of the error message I get now.

Thanks,
Mike
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oldmouldy over 11 years ago

You are missing a newline, any ".model..." statement must be at the start of the line, not within it.
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