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dummy net assignments of pins and shapes in an inherited footprint

mpfleger

Hi all.

So here's a fun one. I have an SMA connector footprint (I've inherited), that includes a shape on the top layer, obstensibly for impedance control reasons. Now here is where things get interesting. I've had to change some of the padstacks to accomodate the more relaxed (read: sane) specs of a fab house. Suddenly the changed padstacks show as having a DRC error. Reverting to the unchanged file, and examining the padstacks; I see they were flagged as "element is on a dummy net", as is the shape that straddles the bunch of them.

How was this ever accomplished? I understand that this will get taken care of when I place the part on a schematic and assign pins to a net, but the why and how seems like it might be important.

I can see no mechanism in the symbol editor to do this. I've even tried the enved command, followed by enabling logic_edit_enabled as I found discussed online, but this didn't result in anything helpful in menus, nor a working "net logic" command, as I suspect this is specific to Allegro proper, not the symbol editor. The .dra files appear to be some vulgar binary format, so no clues are evident in a text editor :(

I can find all sorts of peripheral issues, but nothing in my forum searching addressed this exact issue. Can someone please shed some light on how this was done?

Thanks a bunch in advance,

-Mike 

  • chads108

     At the footprint level (.dra), Allegro has no net intelligence.  Hense the "dummy" net you see.  DRC's will oft times be generated because it really cannot rectify via to shape, pin to shape, or anything else based on nets.  As you stated, these will be rectified once the footprint is placed and a netlist is behind it.  In your case, the shape will assume the net of the pins it overlaps (assuming they are all attached to the same net).

     Chad

  • mpfleger

    Yeah; this is pretty much what I gathered. It's just a bit maddening to see one pin, that magically has retained its "dummy net" status, be the only one of the group that doesn't have a DRC flag =/

    It would be nice to know how that was done in the first place.

    Cheers,

    M 

  • mcatramb91

    I guess they could of waived the drcs at the symbol level so they didn't see them.  Once the padstacks are replaced drcs will came back.

    The waived drc status won't transfer to the design level, when you place the part, so you will see DRCs again unless the pins are the same net then the shape will adopt the net name.

    Hope this helps,
    Mike Catrambone

  • chads108

     Actually, I think it is purely luck that you dont have one for every pin.  I have found over the years, that it is very random that a pin will actually not have a DRC error, but every once in a while it happens.  If you turn off your DRC's, you won't see them:-)

    Chad

  • mpfleger

    LOL!

    Yeah - I suppose it could be worse :D

    While this discussion was going (and between meetings); I left the DRC flags in place and updated my design to use the new "improved" symbol, and as expected; they all went away as soon as everything got attached to signal gnd ;)

    Was this maybe a feature that existed in a previous version of Performance? The symbol in question originally came from a Xilinx design file (it happened to be Allegro), and whoever did the EDA work for them...

    Thanks for the thoughts!

    -M

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