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Keep power nets separate in a hiearchical design

Mattias J
Hello,

Say that I instantiate the same block four times in a schematic, I’m using the SUBDESING_SUFFIX attribute to keep the same location value in each instance, for example, R1 becomes R1CH1 in channel 1, R1CH2 in channel 2 and so forth. Even though all four blocks are identical I want to use separate voltage nets for each instance. Each block has, let’s say, five schematic pages where one of these pages contains the circuitry for generating the desired voltages. The voltages is supposed to reach the other four pages in the block but not out of the instance.

Here is my dilemma/question. I have used global power ports but now I realize that all power nets are merged together in the netlist since they are global. That was not what I wanted to achieve. How can I solve this dilemma? Should I use off-page connectors instead or can I attach some kind of property to the power ports to keep them in each instance?
  • Johan J

     Hello Mattias,

    If you want to have the power net internal in the block only, you schould NOT user any power symbols. These symbols, with the property HDL_POWER, creates a global signal.

    So use a offpage symbol, for connecting the signal by name inside the block and a IO port for get the power signal into the block.

    I hope this gives you a hint of how you can do this.

     

    Regards,

    Johan Javinder

  • Mattias J

    Hello,

    Thank you for your advice. It worked perfectly.

    Best regards,
    Mattias Johansson

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