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bare die on pcb

arummler
arummler over 11 years ago

Hello,

I have a question similar to the one posed in www.cadence.com/.../20786.aspx .

In my design I will have bare silicon chips directly mounted on the pcb (flex pcb) in a rather complex 3d setup. Those chips have wirebond pads which will be naturally connected by wirebonds to the corresponding pads on the flex. What is the best way to proceed? From what I have found, I suppose I have to create a new part in the part designer with a completely self drawn footprint for each chip and to define the wirebond pads together with a wirebond layer in their padstacks? I searched through the documentation but did not find anything resembling exactly this situation. I would be grateful if someone could point me to an appropriate example.

Thank you very much.

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  • arummler
    arummler over 11 years ago

    Just to bump the thread up. I am still searching for a solution for a COB (chip on board) design, where the die is wirebonded directly to wirebond pads on the pcb. Has anybody here used such a design before?

    In the moment I see two solutions:

    1. Create a new part with a footprint where the die wirebond pads are put such for orientation on a mechanics layer and the corresponding pcb wirebond  pads are defined by the physical pins. This basically works, but has the disadvantage that the whole wirebond connection has to be made "manually"  without any checks. Furthermore, as it is a workaround things like the 3d view don't show the situation properly.
    2. Another idea I had, but I do not know whether it is workable includes creating the die (actually with the from geometry editor) in the package designer, to pull the wirebonds to wirebond pads which are placed on the tip conductive layer. If such an mcm could be converted into a footprint somehow and attached to a package in the part developer, then by placing it on the pcb everything should behave properly. Unfortunately, I have not found any possibility to do that conversion and I am not even sure whether it is not a completely stupid idea.

    Thank you for your input. Sorry for the naive questions but I am a complete beginner regarding the Cadence package.

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  • RTMORA2
    RTMORA2 over 11 years ago
    The Cadence Allegro User Guide Getting Started with Physical Design and Allegro Packager Designer have information about Wire Bond parts.  I don’t use their methods however.

    I have 500-600 pin dies on all many of my designs. I inherited the design process from a previous designer. The die outline with die pads come in as dxf files. I load these into my part design and place on the Package Geometry Assembly Top subclass. I create a WireBond subclass in which I will draw straight lines from the die pad to the bond pad that will be in the pcb. This will visually help me keep the wires from crossing.  I confer with the assembly engineers as to the length of these wires. Be very certain of the pin numbering from the part manufacturer and your bond pad pin numbers match up.  Usually the bond pad to bond pad spacing is .1mm or less, so I have a constraint region to accommodate the tighter pad spacing. I also get an excel spreadsheet indicating die pin functions and or power ground pins. These bond pads are usually grouped together side in one or ever two rows. Still the wires should not cross.  Give yourself extra time, since there will be tedious checking.  If possible get someone else to check the part. I have 3 people to check my parts me, myself & I. Above all, have fun.

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