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CMOS ROM Troubleshooting

Thomas Mitchel

Hello,

I am new to the forum and new to Cadence as well. I have designed  both a CMOS and BJT ROM and am trying to perform Gate level simulations with Cadence Allegro. My BJT ROM outputs show correct movement with the inputs, but my CMOS ROM stays at the 1 position for the entire simulation. Is there something special I need to do with my NMOS and PMOS gates to achieve functionality? I have used the Pspice components in Cadence Capture and am running mixed signal testing.

Any help would be greatly appreciated.

Thank you!

  • oldmouldy
    Can you archive your project? File>Archive Project in Capture and create a single zip. Getting one gate of each type to work will probably resolve the issue.
  • Thomas Mitchel
    Thank you for your response. I am not able to Archive the project, but there is an export option. I've been looking at this issue for many weeks and cannot find the problem. I did make some progress I believe, and have received two redlines on my net alias outputs.
  • oldmouldy
    Capture has a function to Archive PSpice projects, select the DSN file in the Project Manager Window and then File>Archive Project, there is an option to create a single ZIP which will contain you project and simulation settings for investigation, the ZIP can be attached to the forum. IF you are running a digital, "state", simulation, Red Line results in the Probe Window usually mean a node with an unknown state somewhere in the design, any unknown input will often set all output nodes to unknown, for example.
  • Thomas Mitchel

    I was to create a ZIP file with the instructions you gave me. I also created a simplified version of the ROM with just a P-type transistor and a N-type with a clock and receive the same results. I have uploaded my design to the post. Thank you for the help so far!CMOS Troubleshoot-2015-02-11T00-08.zip

  • Thomas Mitchel
    You may also notice that I have inverters placed at the bottom of the ROM output as well. With out these, the net aliases did not show up during gate level simulations. I am working to resolve this issue as well but more concerned with the one at hand.
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