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pin pairs added to wrong match group

spirentgabe

I'm using Allegro 16.6 S042.  I have a DDR4 address bus with a driver, 3 receivers and a termination resistor.  I want the bus to be matched length to each receiver.  To do this, first I create the constraint (relative propagation delay) and topology for a single net in SigXplorer.  There are three constraints, one per receiver.  I create a net class containing all the address nets.  I create an ECSet with three ECSM match groups.  Then I apply the ECSet to the net class.  This correctly generates 3 match groups and all the pin pairs for driver.receiver1, driver.receiver2 and driver.receiver3.  However, the problem is that some of the pin pairs are in the wrong group.  For example, the match group for receiver1 should have all pin pairs from driver to receiver1 but some are from driver to receiver2.  The correct number of nets are in the match group, like address bit 0 will have the right pin pair but address bit 1 will be the wrong pin pair.

How do I move the pin pairs around between match groups?  Since they are auto-generated, they won't let me edit them.

thanks!

  • mcatramb91

    Hello,

    Try setting the Topology Mapping Mode to "Pinuse and Refdes".  This can be done in SigXP or from inside of Constraint Manager Electrical Constraints Set folder under the Routing > Wiring worksheet.  Unfortunately, if this problem occurs on nets where the RefDes don't match the Topology then you would need to rename the RefDes in the Topology to match the nets it is being applied to.

    Hope this helps
    Mike Catrambone

  • spirentgabe

    Thanks for the reply.  I tried your suggestion but it didn't work.  It doesn't error, but it doesn't setup the groups correctly either.  Here's the log from two different nets.

    Net 40-001485-101_A C1_ANA_DDR4B_CK_NEG Schedule: Default

    Mapping Pins of Cset: C1_ANA_DDR4B_ADR0
    Mapping Mode: Pinuse and Refdes

    Cset end point Xnet end point mapping mode
    -------------------------- -------------------------- ------------
    40-001485-101_A R1049.2 40-001485-101_A R1048.2 Pinuse
    40-001485-101_A U1009.P3 40-001485-101_A U1008.K8 Buffer Model
    40-001485-101_A U1001.AV24 40-001485-101_A U1001.AV22 Refdes
    40-001485-101_A U1008.P3 40-001485-101_A U1009.K8 Buffer Model
    40-001485-101_A U1007.P3 40-001485-101_A U1007.K8 Refdes
    Relative Prop Delay: GLOBAL group C1_ANA_DDR4B_U1009_C1_ANA_DDR4B_ADDR 40-001485-101_A U1001.AV22 to 40-001485-101_A U1008.K8 delta=0 MIL tol=50 MIL
    Relative Prop Delay: GLOBAL group C1_ANA_DDR4B_U1008_C1_ANA_DDR4B_ADDR 40-001485-101_A U1001.AV22 to 40-001485-101_A U1009.K8 delta=0 MIL tol=50 MIL
    Relative Prop Delay: GLOBAL group C1_ANA_DDR4B_U1007_C1_ANA_DDR4B_ADDR 40-001485-101_A U1001.AV22 to 40-001485-101_A U1007.K8 delta=0 MIL tol=50 MIL
    Max Via Count: 7
    Total Etch Length: min= max=4000MIL


    *******************************************


    Net 40-001485-101_A C1_ANA_DDR4B_ADR14 Schedule: Default

    Mapping Pins of Cset: C1_ANA_DDR4B_ADR0
    Mapping Mode: Pinuse and Refdes

    Cset end point Xnet end point mapping mode
    -------------------------- -------------------------- --------
    40-001485-101_A R1049.2 40-001485-101_A R1072.2 Pinuse
    40-001485-101_A U1009.P3 40-001485-101_A U1009.L2 Refdes
    40-001485-101_A U1001.AV24 40-001485-101_A U1001.AN23 Refdes
    40-001485-101_A U1008.P3 40-001485-101_A U1008.L2 Refdes
    40-001485-101_A U1007.P3 40-001485-101_A U1007.L2 Refdes
    Relative Prop Delay: GLOBAL group C1_ANA_DDR4B_U1009_C1_ANA_DDR4B_ADDR 40-001485-101_A U1001.AN23 to 40-001485-101_A U1009.L2 delta=0 MIL tol=50 MIL
    Relative Prop Delay: GLOBAL group C1_ANA_DDR4B_U1008_C1_ANA_DDR4B_ADDR 40-001485-101_A U1001.AN23 to 40-001485-101_A U1008.L2 delta=0 MIL tol=50 MIL
    Relative Prop Delay: GLOBAL group C1_ANA_DDR4B_U1007_C1_ANA_DDR4B_ADDR 40-001485-101_A U1001.AN23 to 40-001485-101_A U1007.L2 delta=0 MIL tol=50 MIL
    Max Via Count: 7
    Total Etch Length: min= max=4000MIL

    I can't figure out why U1008 and U1009  use buffer model for the first net but Refdes for the second.  I want it to use Refdes for all.  Oddly enough, the second net does use Refdes for all and I'm not sure why.  I also couldn't set the buffer model for U1008/U1009 for some reason.  I was trying to fake it out by setting them to different models but it just won't let me assign anything to it.

    I tried using Refdes for the mapping topology and that errored out.  Here is the log from that:

    Mapping Pins of Cset: C1_ANA_DDR4B_ADR0
    Mapping Mode: Refdes
    *ERROR: Unable to find a mapping for the following Xnet pins:
    40-001485-101_A R1048.2 40-001485-101_A U1008.K8 40-001485-101_A U1009.K8

    Cset end point Group Buffer model Value net# Mapped To Mapping Mode
    -------------------------- -------- -------------------- ------ ---- -------------------------- ------------
    40-001485-101_A U1001.AV24 IO CDSDefaultIO_2p5v NONE 0 40-001485-101_A U1001.AV22 Refdes
    40-001485-101_A R1049.2 discrete NONE 59 Ohm 0
    40-001485-101_A U1007.P3 receiver CDSDefaultInput_2p5v NONE 0 40-001485-101_A U1007.K8 Refdes
    40-001485-101_A U1008.P3 receiver CDSDefaultInput_2p5v NONE 0
    40-001485-101_A U1009.P3 receiver CDSDefaultInput_2p5v NONE 0

    Xnet end point Group Buffer model Value net# Mapped To Mapping Mode
    -------------------------- -------- -------------------- ------ ---- -------------------------- ------------
    40-001485-101_A U1001.AV22 IO CDSDefaultIO_2p5v NONE 0 40-001485-101_A U1001.AV24 Refdes
    40-001485-101_A R1048.2 discrete 10-004895_59OHM 59 Ohm 0
    40-001485-101_A U1007.K8 receiver CDSDefaultInput_2p5v NONE 0 40-001485-101_A U1007.P3 Refdes
    40-001485-101_A U1008.K8 receiver CDSDefaultInput_2p5v NONE 0
    40-001485-101_A U1009.K8 receiver CDSDefaultInput_2p5v NONE 0
    *ERROR: unable to set relative propagation delay constraints on net due to mapping error.
    Max Via Count: 7
    Total Etch Length: min= max=4000MIL

    I don't know why the buffer model for R1049 is NONE, it's clearly set to 10-004895_59OHM when I look in the PCB Editor.  I also don't know why the U1008/U1009 can't be mapped.

    Any thoughts?  Suggestions?

    thanks again,

    gabe

  • DLark

    Try Logic > Net Schedule for problem nets (Allegro scheduled nets by shortest way).

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