Via holes display incorrectly?

Slight mistake above, I am using version 16.6, not 16.3.

Simple question, complex answer. First, if you do a show element on the via it should show the type as Through Plated and the padstack is defined from TOP to BOTTOM. Second, it will also give you the net name that should match with both shapes and be an actual net name, not dummy net. Third, a plated via should have larger pads than the drill size for manufacturability. Here are some guidelines to create a basic via. In the padstack designer, Type should be "Through" and Drill diameter is what you need (let's make it 20 mils). On the Layers tab, enter "Circle" for Geometry and drill size + 15 mils (35 mils) on layers TOP, DEFAULT INTERNAL, BOTTOM, SOLDERMASK_TOP, and SOLDERMASK_BOTTOM. Note that these numbers are just examples. Fourth, display settings are important, but are individual preference. Go to the Setup->Design Parameters Display tab and select "Display plated holes" and "Filled pads". Then look at the differences you see on your board design. When you see the top conductor shape (green) carved out, that doesn't mean that's the size of the drill; do a Show Element on the arc line to see how big it is and compare that to your drill size. Also, go to YouTube and search on "via structures allegro". Good luck.

Hello Randy,

First of all, thank you for your reply, it is really appreciated and it was quite helpful. My problem indeed seemed to be about nets. What I ended up doing was assign the net "Dummy net" to both green and yellow shapes in the screenshot in my initial post, and this resulted in the via hole being carved out into both the green and yellow (top and bottom) conductor shapes. I didn't use another "actual" net name as you suggested since my design does not have any net (I am not sure how, or if, it is possible to add a netlist directly in PCB editor without generating one in capture and importing it). The reason for this is that  I started drawing the board in PCB editor directly without any prior schematic since I am doing a RF PCB without any electronic component on it.

Also in case its useful for someone, I did use the "Display plated holes" option to visualize the drill holes which is quite useful. In my case, the drill holes do match with the carved out region on my conductors. I believe that the two might differ (the drill holes and the hole in the conductor shape) if one has constraints like via to shape minimum distances. For my purposes I set such constraints to 0.

Finally, could you expand on why larger pads than the drill size is required for manufacturability? Taking my example of a through via connecting top and bottom conductor shapes, wouldnt a pad on either layers that is larger than the drill hole just blend with the conductor shape on that layer? In this case wouldn't it result in identical gerber files vs. the case where a pad is defined that is smaller than the drill hole?

Thank you,

Simon

Simon -

If I'm understanding you correctly, you want the via to connect to the shapes on both layers.  In other words, the two shapes and both vias should be electrically connected and have the same netname.  If you are seeing the shapes "carved out" around the via that means the via won't connect to the shapes - it will be isolated from them.

I can think of a couple of ways to achieve this without having a schematic / netlist but here is the one I think will be easiest for you:

First, make sure both shapes are Dynamic shapes

Then move the existing via a known fixed distance so that it is outside of the shapes in question and not touching any other features.

Then copy that via back to the original location making sure that "retain net of vias" is NOT checked.

The copied via should now be in the location you want and it should assume the "dummy net" net name and there should be no clearance in the shapes.  It should then look like this:

Red = top copper shape

Yellow = bottom copper shape

Black in the center of the pad represents the drilled hole

Bright Red = the pad supporting the via on the top and bottom layers

 

The via should be larger than the hole in case it is ever used outside of a shape.  You are correct in thinking that inside the shape, the supporting via pad will be flooded with copper and rendered irrelevant/redundant.  But if you wanted to use it in another area where it would connect to a "normal" trace, you need the pad larger than the hole to allow for proper plating of the hole and interface to the trace.  The extra pad "under" the shape will not cause any problems in the resultant Geber file even though it is not needed. 

 

 

 

Simon,

SevenFortyOneB is exactly right about why a via pad should be larger than the drill size; so it plates properly during the manufacturing process when it's not enclosed in a shape.