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Simulation of clock signal to determine presence of high speed effects

curiousenginr

I have a multi-chip module for which it needs to be determined if the two clock signal shall suffer from high speed effects.

I have the IBIS models of all the parts connected to the clock sources, including IBIS models of the clock soruce themself. I have been able to convert them into PSpice as well.

From perspective of a Cadence expert which is you, what do I do next? What tool do I use? I have information about the PCB which contains the length of the tracks and also their characteristic impedance as well. Also, for one of the two oscillators, the clock output from the oscillator splits into multiple tracks (like a star) and connects to several components. It is expected that this causes an impedance discontinuity and thus can lead to high speed effects.

How do I prove/disprove this in simulation?

  • MikeVeal
    Use the SigXP tool ( Signal Explorer. ) You'll find everything you need in the online documentation.
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