• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design
  3. same net via spacing

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 166
  • Views 13280
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

same net via spacing

Lock2002
Lock2002 over 10 years ago

Is it possible to set a maximum via to via overlap allowed? I have a bunch of vias that are used in thermal tabs and some of the via pads are overlapping. I don't want shut the DRCs off because I would like to keep the via hole to hole controlled.

Thanks

  • Cancel
  • SevenFortyOneB
    SevenFortyOneB over 10 years ago

    I don't know if there is an overlap seting that can be applied, but perhaps modifying the via padstacks to make the pads smaller would work.  You'd then have to remember to use a cline or a shape on other layers to take the place of the pads to support the holes.

     

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information