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Capture: Use hierarchical design to verify cable connector interfaces?

DanInMA

Hello,

I'd like to use Capture's hierarchical feature to create a system consisting of Widget A, Widget B, and a cable connecting the two. The cable has two connectors, each interfaces to one of the Widgets. The goal is to verify continuous nets from Widget A, through the cable interfaces, to Widget B.

If I do this in the traditional approach, hierarchy block connectors are used as the logical interface between the three blocks. I can wire these block connectors to the pins of a connector symbol and logically this works.

However, because I have to manually wire the hierarchy blocks to the connector pins, there is the chance of miswiring the connectors. Is there a better way to create a connector interface such that the connector pins themselves logically mate and can then be checked for net name mismatches?

Thanks a lot,

Dan

  • steve
    Yes - look at Netgroups. You can build the netgroup first and then draw it like you would a bus and connect to the port on the hierarchical blocks. Take a look at https://www.youtube.com/watch?v=VsxU-zlkjAE which is using netgroups in a design but you should get the idea
  • DanInMA

    Hi Steve, thanks for the response.

    I played around with netgroups a bit. Say the cable has a 9pin DSUB at each end. I made a netgroup with 9 signals,  PWR[0..1] and SIGNAL[0..6]. I see that I could route this around like a bus or in block form and I could use this to connect my widgets.

    I'm finding a few issues:

    Should I have created only one bus, SIGNAL[0..8] in order to map that to pins 1-9 on the connector? As of now the nomenclature doesn't relate to the physical pin numbering.

    This by definition creates a cable that is wired "1 to 1". What if I needed to wire each connector on the cable differently?

    I also need to handle the connector interface on the Widgets themselves which would contain PCB mounted connectors and thus require a symbol with a PCB footprint. I could add the symbol and wire it to the signals in the netgroup, but again that is the manual process I'm trying to avoid.

    Having the cable defined as a netgroup instead of a block doesn't allow it to have its own schematic page and might make extracting the information for build/production difficult.

    The problem is basically that I could wire the connector symbols any way I wanted and the DRC would still pass a netlist check because the logical connectors "short circuit" the physical connections to the connector pins in the symbol. I want the DRC to check that pin 1 on the physical connector on Widget A is connected to the same net on the cable and the same net on Widget B through the physical connector interfaces, not just the logical block connector interfaces.

    I would like to verify the 5V net through the connector interfaces such as:

    Widget A Connector Cable Connector 1 Cable Connector 2 Widget B Connector
    Pin 1 Pin 1 Pin 5 Pin 5
    net: 5V net: 5V net: 5V net: 5V

    Verifying it logically is simple, but I'm hoping to find a way to verify the connector interfaces are pinned out correctly as well.

    Thanks again

  • steve
    A full size netgroup might help but it doesn't have to be. You can use the connect to bus option on a group of pins or individual pin which may give you more control but the connection then becomes manual again. Remember this a PCB design tool and not a cable specific tool so it's not going to DRC check for this. You could try and write a Tcl/Tk DRC script to give you what you want. There are some examples under the Configure Custom DRC button...
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