Regarding reference planes

Yes, crossing split power planes in L4 will affect high speed signals on L3. The faster you go, the worse it gets. The easiest thing you can to is avoid this. 

Return current will try to flow in both referenced planes. If you put a gap in one of the planes then you'll have an inductive "bump" at that point in the trace. You will get a reflection - it may or may not be significant. You may get radiation. The return current has to find a path around the gap, which means current flows in a loop.

There are things you might be able to do to mitigate, but they will require careful simulation and may not work depending on how fast your signals are and how fat your stack is.

Basically you want to make the return path on L4 contiguous for the return current. If you have a 3V3 plane and a 5V plane and your HSS crosses a split, then consider a (some) caps at the crossing location. But don't forget the inductance of the cap vias (and the size of the loop created by going up to the surface, through the cap and back down to L4). A cap on the top will be far more effective bridging a plane split on L4 of 16 than a cap on the bottom. The faster the edges of your signal, and the longer the (current bearing part of) the via the less effective this will be. You could add a decoupler from 5V to GND and another from 3V3 to GND, but now the return current has to flow through two caps and four vias, so how about a single cap directly between 5V and 3V3?

Don't forget that you may need to do a similar trick at TX and RX ends as well. If your HSS comes out of a SerDes powered from say 1v8, then you want return currents to get back into the driving chip through the 1V8 or GND pins. But if the HSS references a 5V plane at this point, then the return path into the chip pins is probably convoluted. ie. probably 5V to GND via a decoupler then into the driving chip GND pin. If the 5V decoupler is miles away from the chip SerDes pins, then you have current loops in the return path, which are inductive...

It all a question of speed and scale.

If you're going fast enough to have to worry about this, it's far, far easier to avoid jumping plane splits than it is to worry about all of this. Spend some more time on your stack. Try sandwiching the split planes between two soild GNDs. Look more closely at the layout. TX and RX  chips of a HSS probably share the same supply voltage (and GND) so use the shared supply rail as a reference for the HSS.

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Yes, crossing split power planes in L4 will affect high speed signals on L3. The faster you go, the worse it gets. The easiest thing you can to is avoid this. 

Return current will try to flow in both referenced planes. If you put a gap in one of the planes then you'll have an inductive "bump" at that point in the trace. You will get a reflection - it may or may not be significant. You may get radiation. The return current has to find a path around the gap, which means current flows in a loop.

There are things you might be able to do to mitigate, but they will require careful simulation and may not work depending on how fast your signals are and how fat your stack is.

Basically you want to make the return path on L4 contiguous for the return current. If you have a 3V3 plane and a 5V plane and your HSS crosses a split, then consider a (some) caps at the crossing location. But don't forget the inductance of the cap vias (and the size of the loop created by going up to the surface, through the cap and back down to L4). A cap on the top will be far more effective bridging a plane split on L4 of 16 than a cap on the bottom. The faster the edges of your signal, and the longer the (current bearing part of) the via the less effective this will be. You could add a decoupler from 5V to GND and another from 3V3 to GND, but now the return current has to flow through two caps and four vias, so how about a single cap directly between 5V and 3V3?

Don't forget that you may need to do a similar trick at TX and RX ends as well. If your HSS comes out of a SerDes powered from say 1v8, then you want return currents to get back into the driving chip through the 1V8 or GND pins. But if the HSS references a 5V plane at this point, then the return path into the chip pins is probably convoluted. ie. probably 5V to GND via a decoupler then into the driving chip GND pin. If the 5V decoupler is miles away from the chip SerDes pins, then you have current loops in the return path, which are inductive...

It all a question of speed and scale.

If you're going fast enough to have to worry about this, it's far, far easier to avoid jumping plane splits than it is to worry about all of this. Spend some more time on your stack. Try sandwiching the split planes between two soild GNDs. Look more closely at the layout. TX and RX  chips of a HSS probably share the same supply voltage (and GND) so use the shared supply rail as a reference for the HSS.

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