DRC missing trace through mounting hole?

Thanks OM. I recalled this happening once before and went through my notes - found response from Orcad support stating exactly what you said. I know I updated those settings at that time both here at Sage and at my company TH Designs Inc. I checked both computers and both had the settings back to the default. I'm wondering if one of the more recent updates changed those settings back as I surely didn't change them..........

It is interesting though that when I moved the mounting hole and placed it on top of the trace, there were no errors flagged (due to the settings) BUT when I select the trace, it jumps to provide the CM clearance so it knows the hole is there.

Below is what I received from Orcad last July when I first saw this problem:

You need to check the Analysis Modes (in 16.6-2015 – Setup > Constraint Modes).  With 16.6 some of the Analysis Modes that determine whether violations are being checked for have been set to OFF, no not check.  Cadence was asked with the initial release of version 16.6 to disable a lot of the DRC checks.

In the Analysis Modes make sure that the following DESIGN MODES are set to ON:

• ·         Mech. Pin to mech. Pin
• ·         Mech. Pin to conductor
• ·         Min. metal to metal

Also, in the SPACING MODES you will probably find that not all of the spacing selections have a checkmark in the selection box.  Some may contain a gray square in the box and the Hole selection is blank.  In each of these the rules against the mechanical hole is NOT being checked for.  All of these SPACING MODE selections should have a checkmark in the selection box.

Another one, if you use the SAME NET SPACING rules then you will find in the Analysis Modes that every selection in the SAME NET SPACING MODES are set to blank, or don’t check these rule.

What I suggests to students at my PCB Editor classes is that they really need to go through each of the MODES in this form and make sure that the rule sets that they set in the Constraint manager are truly being checked for in the Analysis modes form.

I hope this helps clarify why you did not get the DRC error.

Thanks OM. I recalled this happening once before and went through my notes - found response from Orcad support stating exactly what you said. I know I updated those settings at that time both here at Sage and at my company TH Designs Inc. I checked both computers and both had the settings back to the default. I'm wondering if one of the more recent updates changed those settings back as I surely didn't change them..........

It is interesting though that when I moved the mounting hole and placed it on top of the trace, there were no errors flagged (due to the settings) BUT when I select the trace, it jumps to provide the CM clearance so it knows the hole is there.

Below is what I received from Orcad last July when I first saw this problem:

You need to check the Analysis Modes (in 16.6-2015 – Setup > Constraint Modes).  With 16.6 some of the Analysis Modes that determine whether violations are being checked for have been set to OFF, no not check.  Cadence was asked with the initial release of version 16.6 to disable a lot of the DRC checks.

In the Analysis Modes make sure that the following DESIGN MODES are set to ON:

• ·         Mech. Pin to mech. Pin
• ·         Mech. Pin to conductor
• ·         Min. metal to metal

Also, in the SPACING MODES you will probably find that not all of the spacing selections have a checkmark in the selection box.  Some may contain a gray square in the box and the Hole selection is blank.  In each of these the rules against the mechanical hole is NOT being checked for.  All of these SPACING MODE selections should have a checkmark in the selection box.

Another one, if you use the SAME NET SPACING rules then you will find in the Analysis Modes that every selection in the SAME NET SPACING MODES are set to blank, or don’t check these rule.

What I suggests to students at my PCB Editor classes is that they really need to go through each of the MODES in this form and make sure that the rule sets that they set in the Constraint manager are truly being checked for in the Analysis modes form.

I hope this helps clarify why you did not get the DRC error.