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2 Layer PCB Design

kapp

Hi All,

I am making the PCB of SI1143 gesture control. I am making the 2 layer PCB , (Top & Bottom). I have three connections along with other connections.

I have a confusion that how can I represent the connection of VCC and ground.

I am giving two voltages to my circuit and one ground . Since in Schematic, I connected the circuit with symbols like VCC and ground. But in PCB editor how can show the connection of VCC and ground ?

How to make the connection of Vcc and ground by Via in PCB editor.

Can somebody suggest me for this as soon as possible? I am stuck at this point.

  • Normally by default the VCC and GND nets are not shown. Try Setup - Constraints - Constraint Manager then go to the Properties tab - Net -General Properties and look for the No Rat column. It will be set to ON for VCC and GND so select the On and change the drop down to Clear. Then the nets should be shown.
  • Thanks for the Reply. I went to route then automatic route. I did fanout. then routing. I got 10 errors in my netHi all,

    I'm experiencing a problem
    when routing through power planes.

    I've setup this simple stackup

    top
    gnd plane
    vcc plane
    bottom

    If the router (manual or auto)
    places a via between top and bottom layers,
    the DRC shows a spacing violation with gnd.


    'Item 1 < DRC ERROR >

    ' Class: DRC ERROR CLASS
    ' Subclass: GND
    ' Origin xy: (1503.56 1230.00)
    '
    ' CONSTRAINT: Shape to Thru Via Spacing
    ' CONSTRAINT SET: DEFAULT
    ' CONSTRAINT TYPE: NET SPACING CONSTRAINTS
    ' Constraint value: 5 MIL
    ' Actual value: 0 MIL


    This happens when the power planes have been etched
    (either before or after routing).


    Why there is no clearance beetwen the via
    and the etched planes?
    How can I avoid this error?
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