Community PCB Design PCB Design Why Hierarchical Variant disabled in Allegro Design Entry...

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 162
  • Views 40980
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Why Hierarchical Variant disabled in Allegro Design Entry HDL 16.6-2015

Jinkai

The User guide PDF suggests three reasons, but doesn't explicitly say how to solve it:

1) "There is no variant information in the lower-level block (reusable block)."

>I have created variant data for my lower level block. I then copy and paste the lower level block's windows folder into the worklib of my main project. Is that enough?

2) "Variants are not defined for the top-level block."

>What does this mean? That I need to create variants for my top-level block as well? Why? I did this, doesn't make a difference.

3) "The block has not been identified for hierarchical variants."

>What does this mean?

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.