• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design
  3. Creating exceptions to keepouts

Stats

  • Locked Locked
  • Replies 4
  • Subscribers 167
  • Views 15524
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Creating exceptions to keepouts

IainFK
IainFK over 9 years ago

Hi all

Using Allegro 16.6, I want to create a via keepout area that will only allow GND vias, and give an error if any other net is in there. Is this possible? This is for an area of the board that will be in contact with the case, so GND vias are fine (and indeed desirable) but anything else presents a shorting risk. There are other occasions where an exception to a keepout would be useful so any ideas would be much appreciated.

Thanks

Iain 

(not Lain)

  • Cancel
  • steve
    steve over 9 years ago
    Sort of - take a look at:- http://orcad.co.uk/images/PDF/net_areas.pdf
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Soundman99
    Soundman99 over 9 years ago

    There is a support case for this, it's called "Allow certain nets only in a route keepout area with no DRCs".  Basically, you go in and create a Physical Spacing constraint set that doesn't allow any etch, and then another that does.  You create a net class with your GND net/s in it.  Then, in your region, you assign the region the no-etch PSC, and on the class that contains your GND net/s, you assign it a PSC that allows etch.  

    I don't know if the link here will work, but this might bring you right to the article on how to do it.

    http://support.cadence.com/wps/myportal/cos/COSHome/viewsolution/!ut/p/a1/tY_NDoIwEISfxbumW0QKx_oTEFCiYqRcDGijRFsIgok-va0x8aSe3NvOfjuzi1KUoFRm1-KQNUUps7PuU2s7xRMTexH4rkNHQIEs_HWAjYAMFMAUAB-Kwq_9DUqfyBcHpiLI28MOQweoG1hLj8R9iAhay7IW6tiV9tpzXoWFPCHW1C3XyrjctYLLJr5VXKn55djIQ3df6NmlPLf61Xkrcl4jhjEBCxz7FTrwxib4gP1oaBCgXmy65jzEEBl_Ca1EAj0m7L7YzmKe3yntdB5aw6Wt/dl5/d5/L2dBISEvZ0FBIS9nQSEh/ 

    ~ Pat

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • IainFK
    IainFK over 9 years ago
    Thanks for the help guys, works fine (if a little convoluted!). The only other aggravation was that I couldn't create a void within the constraint shape (which needed to be like a square doughnut) so had to do it with overlapping shapes.
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • mcatramb91
    mcatramb91 over 9 years ago

    Hi,

    What I have done in the past is to create a Static Shape assigned to GND in the area.

    This would allow GND Vias to contact the shape and DRC Vias which are not connected to GND.

    Hope this helps,
    Mike Catrambone

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information