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Can Cadence export .xdc files for Xilinx Vivado?

xiaoyi594

Hi there,

We are design SCH and PCB involving Xilinx Artix-7 FPGA. As usual, we did pin swap during layout, and then we need to verify the swapped pin assignment in Xilinx Vivado .

We do this manually in the past, Could Cadence directly export the ".xdc" or "tcl" file which can be imported by Vivado?  And how? I am using V16.6 with hotfix 20. Thanks!

I googled and found this link, but its saying "You can now generate .xdc files and Vivado TCL scripts for all the Virtex 7 devices." 

  • oldmouldy
    You have hotfix 20 and the note that you linked to is for hotfix 27, it also relates to the FPGA System Planner product so you would need to get a later hotfix, obviously the latest would work, and get a license for the FPGA System Planner to be able to get this functionality. Since you probably didn't start out development with the FPGA System Planner this may, or may not, be a viable option at this stage in your design.
  • xiaoyi594
    Hi oldmouldy,
    We already start FPGA design, just need to update pin assignment info in Vivado. Suppose we install latest hotfix, could we export xdc files from cadence?
    Thanks.
  • xiaoyi594
    Hi oldmouldy,
    I am glad to found that ORCAD could export UCF file(an older pin configuration format for ISE), and then UCF could be converted to .xdc file in Vivado.
    However, the exported .ucf file only contains pin name and net information. Is there anyway to inlcude IO standard information(such as "LVCMOS33", "LVDS_25") when exporting .ucf from ORCAD? I think there should be somewhere to config this IO standard info into ORCAD Schematics.
  • xiaoyi594
    the operation is In OrCAD Capture try Tools - Export FPGA....choose UCF
  • xiaoyi594
    Hi oldmouldy,
    I tried right click on FPGA symbol and use "Export FPGA", choose UCF or CVS, get "pin number" and "net name" information.
    However, I got no info about pin's direction, io standard... where should I set these attribute for pins in ORCAD, so I can get a more complete .ucf or cvs file which can be imported into Xilinx ISE or Vivado. Thanks, and Merry Christmas!

    (1).Following is excerpt from cvs file, you can see, only Pin Number and Signal Name is exported, other attributes is empty.
    Pin Number, Signal Name, Direction, IO Standard, Drive (mA), Slew Rate, Termination, IOB Delay, Diff Type, Diff Pair, Swap Group
    H12,DDR_BF_RST_N,UNUSED,,,,,,,,
    G10,DDR_BF_DQ4,UNUSED,,,,,,,,
    G9,DDR_BF_DQ2,UNUSED,,,,,,,,

    (2).Following is excerpt from ucf file, also, only Pin Number and Signal Name are exported.
    NET "DDR_BF_RST_N" LOC = "H12";
    NET "DDR_BF_DQ4" LOC = "G10";
    NET "DDR_BF_DQ2" LOC = "G9";
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