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ERC Error: "Output Connected to Bidirectional Port"

kbalaji

Hi,

I am making a hierarchical top-down design in Design Entry CIS v16.6. The root schematic has hierarchical blocks connected by Named Netgroups; the hierarchical pins have been designated as "Bidirectional" with the corresponding Netgroup associated with it. (An indicative image included below)

On descending the hierarchy, the schematic has both inputs and outputs from ICs connecting to the Netgroup port . 

When running the DRC, I get the "Output connected to bidirectional port" error. Since the ports actually represent Netgroups (with inputs and outputs) I was not expecting this kind of  error. Am I missing something? Any assistance in this regard will be greatly appreciated.

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