Running a basis script in Allegro Design Entry HDL causes schematics error

Hello Cadence Community!

I am extensively using automation-generated scripting (*.scr) to automate schematic generation and updating in Allegro Design Entry HDL.

Everything is working well for me, except a quite weird situation:

• If I run a piece of script by copying and pasting inside Allegro Design Entry HDL's integrated Command Console, everything is drawn correctly 
• If I run exactly the same piece of script through the Tools --> Run Script..., instead, the schematic produces an error.

The error I am referring to is the following:

BEFORE RUNNING THE SCRIPT I HAVE THE FOLLOWING:

I USE SCRIPTING TO CONVERT IT INTO THE FOLLOWING:

The lines inside the script are the following:

delete (-5150 4050)
delete (-4850 4050)
wire (-5540 4050) (-4600 4050)
signame (-5520 4050) NEW_SIGNAME__1
paint pink (-5520 4055)
add <ports_lib>ioport (-5590 4050)
mirror (-5590 4050)
delete (-5150 4100)
delete (-4850 4100)
wire (-5540 4100) (-4600 4100)
signame (-5520 4100) NEW_SIGNAME__2
paint pink (-5520 4105)
add <ports_lib>ioport (-5590 4100)
mirror (-5590 4100)

The script does not work well through Tools --> Run Script for the following reason: although cosmetically speaking the result is correct, the errors lies in the fact that one wire gets both netnames associated to it, the other wire gets nothing. To display the issue, here is what happens if I try to move one of the two wires around in the schematic page:

Also, this error happens only to signals/wires/ports (that are connected to components, a reuse block in this case) that are closely spaced between each other (50px on the page grid). No overlapping whatsoever, however, happens among wires/netnames/ports.

Any solution to this is greatly appreciated - thank you in advance for your kind contribution!

Paolo