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micro-via to buried via spacing

Lock2002

I'm having trouble getting Allegro to report a DRC for a micro-via (L1-L2) stacked over a buried via (L2-LX). It will report as a DRC until the center of the micro-via crosses the outer pads edge of the buried via.

  • Anil CAD
    in reply to Lock2002

    This is a tricky Setting in Cadence. When I use HDI in cadence Allegro I follow 2 methods as below

    1) I create stackup Electrical layers+Dielectric layers. if I have 6 layer board, stack up shows 11 layers in visibility pan (6 Electrical layers, 5 Dielectric layers just like in Package Design)

    I define Via pad size in Electrical layers, Only hole size on Dielectric Layers

    I Enable Same net Hole-Hole constraint in Constraint modes, I also set Pad-Pad Connect in Physical Constraints to "Not Allowed" against Dielectric Layers

    Now You can see these DRCs popping up in Dielectric layers

    2)This Method, conventional stackup. If you dont like to insert Dielectric layers in Stack up. I shall define vias as Micro-Vias (all Blind and Buried)

    Enable Same net DRC for Vias-vias as well as Hole-hole in constraint Modes

    In Physical constraints, Pad-Pad connect needs to be set "MicroVias_Microvias_COINCENDENT_ONLY"

    This will ensure Either Full stacked or stagger, no Hole Offset overlap.

    Hope this helps

    Regards,

    Anil Kumar S

  • Lock2002
    in reply to Anil CAD

    For what we pay for Allegro you'd think there would be a more straightforward solution. 

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